# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1495059951 -7200
# Node ID 9e55bb93989ce6711284f141bbaa5afa3691b785
# Parent  3c8c93365e4733bbed3ded57d9e265f2e69aecfb
Test a 48MHz system clock, 24MHz peripheral clock, and 800 x 600 @ 60Hz output
with the 160x256 picture in the centre of the screen, 256 lines doubled to 512.

diff -r 3c8c93365e47 -r 9e55bb93989c vga.S
--- a/vga.S	Wed May 17 23:53:40 2017 +0200
+++ b/vga.S	Thu May 18 00:25:51 2017 +0200
@@ -22,15 +22,15 @@
 
 #define LINE_LENGTH	160	/* pixels */
 
-#define HFREQ_LIMIT	936	/* 30MHz cycles */
-#define HSYNC_START	800	/* 30MHz cycles */
-#define HSYNC_LIMIT	112	/* 30MHz cycles */
+#define HFREQ_LIMIT	643	/* 24MHz cycles */
+#define HSYNC_START	460	/* 24MHz cycles */
+#define HSYNC_LIMIT	64	/* 24MHz cycles */
 #define HSYNC_END	(HSYNC_START + HSYNC_LIMIT)
 
-#define VISIBLE_START	15	/* horizontal lines, back porch end */
-#define VFP_START	527	/* horizontal lines, front porch start */
-#define VSYNC_START	529	/* horizontal lines, front porch end */
-#define VSYNC_END	531	/* horizontal lines, back porch start */
+#define VISIBLE_START	70	/* horizontal lines, back porch end */
+#define VFP_START	592	/* horizontal lines, front porch start */
+#define VSYNC_START	620	/* horizontal lines, front porch end */
+#define VSYNC_END	622	/* horizontal lines, back porch start */
 
 #define SCREEN_SIZE	(40 * 1024)
 
@@ -41,9 +41,7 @@
 
 /*
 Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
-divided by 1, and FRCDIV+PLL selected.
-
-The system clock and peripheral clock are therefore the same.
+divided by 2, and FRCDIV+PLL selected.
 
 The watchdog timer (FWDTEN) is also disabled.
 
@@ -52,19 +50,19 @@
 */
 
 .section .devcfg1, "a"
-.word 0xff7fcfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 0;
+.word 0xff7fdfd9	/* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
 			DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
 
 /*
 Set the FRC oscillator PLL function with an input division of 4, an output
-division of 2, a multiplication of 15, yielding a multiplication of 1.875.
-
-The FRC is apparently at 16MHz and this produces a system clock of 30MHz.
+division of 2, a multiplication of 24, yielding a multiplication of 3.
+
+The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
 */
 
 .section .devcfg2, "a"
-.word 0xfff9ff8b	/* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
-			DEVCFG2<6:4> = FPLLMUL<2:0> = 000;
+.word 0xfff9fffb	/* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
+			DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
 			DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
 
 .text