1.1 --- a/vga.S Sat Nov 04 21:33:58 2017 +0100
1.2 +++ b/vga.S Sat Nov 04 21:47:48 2017 +0100
1.3 @@ -497,8 +497,8 @@
1.4 sw $v1, SET($v0)
1.5
1.6 /*
1.7 - Initialise a line channel.
1.8 - The line channel will be channel 0 (x = 0).
1.9 + Initialise a start channel.
1.10 + The start channel will be channel 0 (x = 0).
1.11
1.12 Specify a priority of 3:
1.13 DCHxCON<1:0> = CHPRI<1:0> = 3
1.14 @@ -512,8 +512,9 @@
1.15 sw $v1, 0($v0)
1.16
1.17 /*
1.18 - Initialise a level reset channel.
1.19 - The reset channel will be channel 1 (x = 1).
1.20 + Initialise line and level reset channels.
1.21 + The line channel will be channel 1 (x = 1).
1.22 + The reset channel will be channel 2 (x = 2).
1.23
1.24 Specify a priority of 3:
1.25 DCHxCON<1:0> = CHPRI<1:0> = 3
1.26 @@ -547,8 +548,9 @@
1.27 sw $v1, 0($v0)
1.28
1.29 /*
1.30 - Initiate reset channel transfer when channel 0 is finished:
1.31 - DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt
1.32 + Initiate line channel transfer when channel 0 is finished:
1.33 + Initiate reset channel transfer when channel 1 is finished:
1.34 + DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 or 1 interrupt
1.35 DCHxECON<4> = SIRQEN = 1
1.36 */
1.37
1.38 @@ -565,17 +567,18 @@
1.39 DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH
1.40 */
1.41
1.42 - la $v0, DCH0CSIZ
1.43 + la $v0, DCH1CSIZ
1.44 li $v1, LINE_LENGTH
1.45 sw $v1, 0($v0)
1.46
1.47 /*
1.48 - The reset channel has a cell size of a single zero byte:
1.49 + The start and reset channels have a cell size of a single zero byte:
1.50 DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1
1.51 */
1.52
1.53 - la $v0, DCH1CSIZ
1.54 li $v1, 1
1.55 +
1.56 + la $v0, DCH0CSIZ
1.57 sw $v1, 0($v0)
1.58
1.59 la $v0, DCH2CSIZ
1.60 @@ -586,12 +589,13 @@
1.61 DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1
1.62 */
1.63
1.64 - la $v0, DCH0SSIZ
1.65 + la $v0, DCH1SSIZ
1.66 li $v1, LINE_LENGTH
1.67 sw $v1, 0($v0)
1.68
1.69 - la $v0, DCH1SSIZ
1.70 li $v1, 1
1.71 +
1.72 + la $v0, DCH0SSIZ
1.73 sw $v1, 0($v0)
1.74
1.75 la $v0, DCH2SSIZ
1.76 @@ -602,25 +606,23 @@
1.77 DCHxSSA = physical(line data address)
1.78 */
1.79
1.80 - la $v0, DCH0SSA
1.81 + la $v0, DCH1SSA
1.82 li $v1, SCREEN_BASE
1.83 sw $v1, 0($v0)
1.84
1.85 /*
1.86 - For the reset channel, a single byte of zero is transferred:
1.87 + For the start and reset channels, a single byte of zero is transferred:
1.88 DCHxSSA = physical(zero data address)
1.89 */
1.90
1.91 - la $v0, DCH1SSA
1.92 - la $v1, fulldata
1.93 + la $v1, zerodata
1.94 li $t8, KSEG0_BASE
1.95 subu $v1, $v1, $t8
1.96 +
1.97 + la $v0, DCH0SSA
1.98 sw $v1, 0($v0)
1.99
1.100 la $v0, DCH2SSA
1.101 - la $v1, zerodata
1.102 - li $t8, KSEG0_BASE
1.103 - subu $v1, $v1, $t8
1.104 sw $v1, 0($v0)
1.105
1.106 /*
1.107 @@ -628,8 +630,9 @@
1.108 DCHxDSIZ<15:0> = CHDSIZ<15:0> = 1
1.109 */
1.110
1.111 + li $v1, 1
1.112 +
1.113 la $v0, DCH0DSIZ
1.114 - li $v1, 1
1.115 sw $v1, 0($v0)
1.116
1.117 la $v0, DCH1DSIZ
1.118 @@ -643,10 +646,11 @@
1.119 DCHxDSA = physical(PORTB)
1.120 */
1.121
1.122 - la $v0, DCH0DSA
1.123 li $v1, PORTB
1.124 li $t8, KSEG1_BASE
1.125 subu $v1, $v1, $t8
1.126 +
1.127 + la $v0, DCH0DSA
1.128 sw $v1, 0($v0)
1.129
1.130 la $v0, DCH1DSA
1.131 @@ -682,7 +686,7 @@
1.132 li $v1, (0b11 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 1 */
1.133 sw $v1, SET($v0)
1.134
1.135 - /* Enable line channel. */
1.136 + /* Enable start channel. */
1.137
1.138 la $v0, DCH0CON
1.139 li $v1, 0b10000000
1.140 @@ -694,9 +698,6 @@
1.141 zerodata:
1.142 .word 0
1.143
1.144 -fulldata:
1.145 -.word 255
1.146 -
1.147
1.148
1.149 /* Utilities. */
1.150 @@ -979,21 +980,15 @@
1.151
1.152 /* Update the source address. */
1.153
1.154 - la $v0, DCH0SSA
1.155 + la $v0, DCH1SSA
1.156 sw $s2, 0($v0)
1.157
1.158 - /* Enable the line channel for timer event transfer initiation. */
1.159 + /* Enable the start channel for timer event transfer initiation. */
1.160
1.161 la $v0, DCH0ECON
1.162 li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
1.163 sw $v1, SET($v0)
1.164
1.165 - /* Disable the timer interrupt during the visible period. */
1.166 -
1.167 - la $v0, IEC0
1.168 - li $v1, (1 << 9)
1.169 - sw $v1, CLR($v0) /* T2IE = 0 */
1.170 -
1.171 _vbp_active_ret:
1.172 jr $ra
1.173 nop
1.174 @@ -1013,12 +1008,6 @@
1.175
1.176 la $s1, vfp_active
1.177
1.178 - /* Re-enable the timer interrupt after the visible period. */
1.179 -
1.180 - la $v0, IEC0
1.181 - li $v1, (1 << 9)
1.182 - sw $v1, SET($v0) /* T2IE = 1 */
1.183 -
1.184 _visible_active_ret:
1.185 jr $ra
1.186 nop
1.187 @@ -1035,7 +1024,7 @@
1.188 bne $s1, $v0, _visible_update_address
1.189 nop
1.190
1.191 - /* Disable the line channel. */
1.192 + /* Disable the start channel. */
1.193
1.194 la $v0, DCH0ECON
1.195 li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 0 */
1.196 @@ -1074,7 +1063,7 @@
1.197
1.198 /* Update the source address. */
1.199
1.200 - la $v0, DCH0SSA
1.201 + la $v0, DCH1SSA
1.202 sw $s2, 0($v0)
1.203
1.204 _visible_update_ret: