1.1 --- a/pic32.h Wed May 10 00:08:19 2017 +0200
1.2 +++ b/pic32.h Wed May 10 00:14:50 2017 +0200
1.3 @@ -11,6 +11,9 @@
1.4 #define T1CON 0xBF800600
1.5 #define TMR1 0xBF800610
1.6 #define PR1 0xBF800620
1.7 +#define T2CON 0xBF800800
1.8 +#define TMR2 0xBF800810
1.9 +#define PR2 0xBF800820
1.10
1.11 #define PMCON 0xBF807000
1.12 #define PMMODE 0xBF807010
1.13 @@ -29,6 +32,7 @@
1.14 #define IEC0 0xBF881060
1.15 #define IEC1 0xBF881070
1.16 #define IPC1 0xBF8810A0
1.17 +#define IPC2 0xBF8810B0
1.18 #define IPC7 0xBF881100
1.19 #define IPC8 0xBF881110
1.20 #define IPC10 0xBF881130
2.1 --- a/vga.S Wed May 10 00:08:19 2017 +0200
2.2 +++ b/vga.S Wed May 10 00:14:50 2017 +0200
2.3 @@ -100,7 +100,7 @@
2.4
2.5 /* Initialise timer. */
2.6
2.7 - jal init_timer1
2.8 + jal init_timer2
2.9 nop
2.10
2.11 /* Initialise PMP. */
2.12 @@ -189,7 +189,7 @@
2.13
2.14 la $v0, IFS0
2.15 lw $v1, 0($v0)
2.16 - andi $v1, $v1, (1 << 4) /* T1IF */
2.17 + andi $v1, $v1, (1 << 9) /* T2IF */
2.18 beqz $v1, irq_next
2.19 nop
2.20
2.21 @@ -214,7 +214,7 @@
2.22 /* Clear the timer interrupt condition. */
2.23
2.24 la $v0, IFS0
2.25 - li $v1, (1 << 4) /* IFS0<4> = T1IF = 0 */
2.26 + li $v1, (1 << 9) /* IFS0<9> = T2IF = 0 */
2.27 sw $v1, CLR($v0)
2.28
2.29 irq_next:
2.30 @@ -397,38 +397,38 @@
2.31
2.32 /* Initialisation routines. */
2.33
2.34 -init_timer1:
2.35 +init_timer2:
2.36
2.37 - /* Initialise Timer1 interrupt. */
2.38 + /* Initialise Timer2 interrupt. */
2.39
2.40 - la $v0, T1CON
2.41 - sw $zero, 0($v0) /* T1CON = 0 */
2.42 + la $v0, T2CON
2.43 + sw $zero, 0($v0) /* T2CON = 0 */
2.44 nop
2.45
2.46 - la $v0, TMR1
2.47 - sw $zero, 0($v0) /* TMR1 = 0 */
2.48 - la $v0, PR1
2.49 + la $v0, TMR2
2.50 + sw $zero, 0($v0) /* TMR2 = 0 */
2.51 + la $v0, PR2
2.52 li $v1, HFREQ_LIMIT
2.53 - sw $v1, 0($v0) /* PR1 = HFREQ_LIMIT */
2.54 + sw $v1, 0($v0) /* PR2 = HFREQ_LIMIT */
2.55
2.56 - /* Initialise Timer1 interrupt. */
2.57 + /* Initialise Timer2 interrupt. */
2.58
2.59 la $v0, IFS0
2.60 - li $v1, (1 << 4)
2.61 - sw $v1, CLR($v0) /* IFS0CLR: T1IF = 0 */
2.62 - la $v0, IPC1
2.63 + li $v1, (1 << 9)
2.64 + sw $v1, CLR($v0) /* IFS0CLR: T2IF = 0 */
2.65 + la $v0, IPC2
2.66 li $v1, (7 << 2)
2.67 - sw $v1, SET($v0) /* IPC1SET: T1IP = 7 */
2.68 - la $v0, IPC1
2.69 + sw $v1, SET($v0) /* IPC1SET: T2IP = 7 */
2.70 + la $v0, IPC2
2.71 li $v1, 3
2.72 - sw $v1, SET($v0) /* IPC1SET: T1IS = 3 */
2.73 + sw $v1, SET($v0) /* IPC1SET: T2IS = 3 */
2.74 la $v0, IEC0
2.75 - li $v1, (1 << 4)
2.76 - sw $v1, SET($v0) /* IEC0SET: T1IE = 1 */
2.77 + li $v1, (1 << 9)
2.78 + sw $v1, SET($v0) /* IEC0SET: T2IE = 1 */
2.79
2.80 /* Start timer. */
2.81
2.82 - la $v0, T1CON
2.83 + la $v0, T2CON
2.84 li $v1, (1 << 15) /* ON = 1 */
2.85 sw $v1, SET($v0) /* T1CONSET: ON = 1 */
2.86