1.1 --- a/README.txt Sat Nov 04 17:07:15 2017 +0100
1.2 +++ b/README.txt Sat Nov 04 17:47:52 2017 +0100
1.3 @@ -38,8 +38,8 @@
1.4 D2/RB2 6 23
1.5 D3/RB3 7 22 RB11/PGEC2
1.6 8 21 RB10/PGEC3
1.7 - RA2 9 20
1.8 - CLKO/RA3 10 19
1.9 + REFCLKO/RA2 9 20
1.10 + RA3 10 19
1.11 D4/RB4 11 18 RB9
1.12 12 17 RB8
1.13 13 16 RB7/D7
1.14 @@ -50,7 +50,7 @@
1.15 Clock Output Routing
1.16 --------------------
1.17
1.18 -CLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
1.19 +REFCLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
1.20 data signals then routed through the flip-flop as follows:
1.21
1.22 MR# 1 \/ 20 VCC
1.23 @@ -62,7 +62,7 @@
1.24 in D2/D2 7 14 D5/D5 in
1.25 in D3/D3 8 13 D4/D4 in
1.26 out D3/Q3 9 12 Q4/D4 out
1.27 - GND 10 11 CP/CLKO in
1.28 + GND 10 11 CP/REFCLKO in
1.29
1.30 MR# is kept at a high level. All out signals are then supplied to the
1.31 analogue circuit provided below.
2.1 --- a/vga.S Sat Nov 04 17:07:15 2017 +0100
2.2 +++ b/vga.S Sat Nov 04 17:47:52 2017 +0100
2.3 @@ -40,8 +40,7 @@
2.4 */
2.5
2.6 .section .devcfg1, "a"
2.7 -.word 0xff7fd8d9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
2.8 - DEVCFG1<10> = OSCIOFNC = 0; DEVCFG1<9:8> = POSCMOD<1:0> = 00;
2.9 +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
2.10 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
2.11
2.12 /*
2.13 @@ -122,6 +121,9 @@
2.14 jal init_io_pins
2.15 nop
2.16
2.17 + jal init_refclk_pins
2.18 + nop
2.19 +
2.20 /* Initialise the status register. */
2.21
2.22 jal init_interrupts
2.23 @@ -382,6 +384,42 @@
2.24
2.25
2.26
2.27 +/*
2.28 +Clock output initialisation. The peripheral clock divided by 2 is output via the
2.29 +CLKO pin to drive a flip-flop.
2.30 +*/
2.31 +
2.32 +init_refclk_pins:
2.33 + /* Change the output clock frequency. */
2.34 +
2.35 + la $v0, REFOCON
2.36 + li $v1, (0b1001001 << 9)
2.37 + sw $v1, SET($v0) /* REFOCON<15> = ON = 1; REFOCON<12> = OE = 1; REFOCON<9> = DIVSWEN = 1 */
2.38 +
2.39 +_refclk_wait:
2.40 + lw $v1, 0($v0)
2.41 + andi $v1, $v1, (1 << 8) /* REFOCON<8> = ACTIVE */
2.42 + bnez $v1, _refclk_wait
2.43 + nop
2.44 +
2.45 + li $v1, 0b1111 /* ROSEL<3:0> = 0000 */
2.46 + sw $v1, CLR($v0)
2.47 + li $v1, 0b0001 /* ROSEL<3:0> = 0001 (PBCLK) */
2.48 + sw $v1, SET($v0)
2.49 +
2.50 + /*
2.51 + The RODIV and ROTRIM values should be zero by default, yielding a
2.52 + frequency of half the input indicated by ROSEL.
2.53 + */
2.54 +
2.55 + li $v1, (1 << 9) /* REFOCON<9> = DIVSWEN = 0 */
2.56 + sw $v1, CLR($v0)
2.57 +
2.58 + jr $ra
2.59 + nop
2.60 +
2.61 +
2.62 +
2.63 init_io_pins:
2.64 /* Unlock the configuration register bits. */
2.65