1.1 --- a/vga.S Mon Nov 06 18:24:04 2017 +0100
1.2 +++ b/vga.S Mon Nov 06 19:12:01 2017 +0100
1.3 @@ -814,19 +814,6 @@
1.4 la $v0, DCH0INT
1.5 lw $v1, 0($v0)
1.6 andi $v1, $v1, (1 << 3) /* CHBCIF */
1.7 - beqz $v1, irq_dma_next
1.8 - nop
1.9 -
1.10 - /* Clear the block transfer completion interrupt flag. */
1.11 -
1.12 - sw $v1, CLR($v0)
1.13 -
1.14 -irq_dma_next:
1.15 - /* Test the block transfer completion interrupt flag. */
1.16 -
1.17 - la $v0, DCH1INT
1.18 - lw $v1, 0($v0)
1.19 - andi $v1, $v1, (1 << 3) /* CHBCIF */
1.20 beqz $v1, irq_exit
1.21 nop
1.22