1.1 --- a/vga.S Sat Nov 04 17:47:52 2017 +0100
1.2 +++ b/vga.S Sat Nov 04 21:33:58 2017 +0100
1.3 @@ -481,13 +481,13 @@
1.4 /* Disable DMA interrupts. */
1.5
1.6 la $v0, IEC1
1.7 - li $v1, (3 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 0 */
1.8 + li $v1, (0b111 << 28) /* IEC1<30:28> = DMA2IE, DMA1IE, DMA0IE = 0 */
1.9 sw $v1, CLR($v0)
1.10
1.11 /* Clear DMA interrupt flags. */
1.12
1.13 la $v0, IFS1
1.14 - li $v1, (3 << 28) /* IFS1<29:28> = DMA1IF, DMA0IF = 0 */
1.15 + li $v1, (0b111 << 28) /* IFS1<30:28> = DMA2IF, DMA1IF, DMA0IF = 0 */
1.16 sw $v1, CLR($v0)
1.17
1.18 /* Enable DMA. */
1.19 @@ -529,6 +529,10 @@
1.20 li $v1, 0b1100011
1.21 sw $v1, 0($v0)
1.22
1.23 + la $v0, DCH2CON
1.24 + li $v1, 0b1100011
1.25 + sw $v1, 0($v0)
1.26 +
1.27 /*
1.28 Initiate channel transfers when the initiating interrupt condition
1.29 occurs:
1.30 @@ -552,6 +556,10 @@
1.31 li $v1, (60 << 8) | (1 << 4)
1.32 sw $v1, 0($v0)
1.33
1.34 + la $v0, DCH2ECON
1.35 + li $v1, (61 << 8) | (1 << 4)
1.36 + sw $v1, 0($v0)
1.37 +
1.38 /*
1.39 The line channel has a cell size of the number bytes in a line:
1.40 DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH
1.41 @@ -570,6 +578,9 @@
1.42 li $v1, 1
1.43 sw $v1, 0($v0)
1.44
1.45 + la $v0, DCH2CSIZ
1.46 + sw $v1, 0($v0)
1.47 +
1.48 /*
1.49 The source has a size identical to the cell size:
1.50 DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1
1.51 @@ -583,6 +594,9 @@
1.52 li $v1, 1
1.53 sw $v1, 0($v0)
1.54
1.55 + la $v0, DCH2SSIZ
1.56 + sw $v1, 0($v0)
1.57 +
1.58 /*
1.59 The source address is the physical address of the line data:
1.60 DCHxSSA = physical(line data address)
1.61 @@ -598,6 +612,12 @@
1.62 */
1.63
1.64 la $v0, DCH1SSA
1.65 + la $v1, fulldata
1.66 + li $t8, KSEG0_BASE
1.67 + subu $v1, $v1, $t8
1.68 + sw $v1, 0($v0)
1.69 +
1.70 + la $v0, DCH2SSA
1.71 la $v1, zerodata
1.72 li $t8, KSEG0_BASE
1.73 subu $v1, $v1, $t8
1.74 @@ -615,6 +635,9 @@
1.75 la $v0, DCH1DSIZ
1.76 sw $v1, 0($v0)
1.77
1.78 + la $v0, DCH2DSIZ
1.79 + sw $v1, 0($v0)
1.80 +
1.81 /*
1.82 The destination address is the physical address of PORTB:
1.83 DCHxDSA = physical(PORTB)
1.84 @@ -629,6 +652,9 @@
1.85 la $v0, DCH1DSA
1.86 sw $v1, 0($v0)
1.87
1.88 + la $v0, DCH2DSA
1.89 + sw $v1, 0($v0)
1.90 +
1.91 /*
1.92 Use the block transfer completion interrupt to indicate when the source
1.93 address can be updated.
1.94 @@ -638,18 +664,22 @@
1.95 li $v1, (1 << 19) /* CHBCIE = 1 */
1.96 sw $v1, 0($v0)
1.97
1.98 + la $v0, DCH1INT
1.99 + li $v1, (1 << 19) /* CHBCIE = 1 */
1.100 + sw $v1, 0($v0)
1.101 +
1.102 /* Enable interrupt for address updating. */
1.103
1.104 la $v0, IPC10
1.105 - li $v1, 0b11111 /* DMA0IP, DMA0IS = 0 */
1.106 + li $v1, 0b1111100011111 /* DMA1IP, DMA1IS, DMA0IP, DMA0IS = 0 */
1.107 sw $v1, CLR($v0)
1.108
1.109 la $v0, IPC10
1.110 - li $v1, 0b11111 /* DMA0IP = 7, DMA0IS = 3 */
1.111 + li $v1, 0b1111100011111 /* DMA1IP, DMA0IP = 7, DMA1IS, DMA0IS = 3 */
1.112 sw $v1, SET($v0)
1.113
1.114 la $v0, IEC1
1.115 - li $v1, (1 << 28) /* IEC1<28> = DMA0IE = 1 */
1.116 + li $v1, (0b11 << 28) /* IEC1<29:28> = DMA1IE, DMA0IE = 1 */
1.117 sw $v1, SET($v0)
1.118
1.119 /* Enable line channel. */
1.120 @@ -664,6 +694,9 @@
1.121 zerodata:
1.122 .word 0
1.123
1.124 +fulldata:
1.125 +.word 255
1.126 +
1.127
1.128
1.129 /* Utilities. */
1.130 @@ -803,7 +836,7 @@
1.131
1.132 la $v0, IFS1
1.133 lw $v1, 0($v0)
1.134 - li $t8, (1 << 28) /* DMA0IF */
1.135 + li $t8, (0b11 << 28) /* DMA1IF, DMA0IF */
1.136 and $v1, $v1, $t8
1.137 beqz $v1, irq_exit
1.138 nop
1.139 @@ -817,6 +850,19 @@
1.140 la $v0, DCH0INT
1.141 lw $v1, 0($v0)
1.142 andi $v1, $v1, (1 << 3) /* CHBCIF */
1.143 + beqz $v1, irq_dma_next
1.144 + nop
1.145 +
1.146 + /* Clear the block transfer completion interrupt flag. */
1.147 +
1.148 + sw $v1, CLR($v0)
1.149 +
1.150 +irq_dma_next:
1.151 + /* Test the block transfer completion interrupt flag. */
1.152 +
1.153 + la $v0, DCH1INT
1.154 + lw $v1, 0($v0)
1.155 + andi $v1, $v1, (1 << 3) /* CHBCIF */
1.156 beqz $v1, irq_exit
1.157 nop
1.158