2.1 --- a/vga.S Sat Nov 04 21:47:48 2017 +0100
2.2 +++ b/vga.S Tue Nov 07 14:04:29 2017 +0100
2.3 @@ -284,8 +284,6 @@
2.4 la $v0, IPC2
2.5 li $v1, 0b11111
2.6 sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
2.7 -
2.8 - la $v0, IPC2
2.9 li $v1, 0b11111
2.10 sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
2.11
2.12 @@ -662,6 +660,7 @@
2.13 mfc0 $t3, CP0_STATUS
2.14 li $t4, ~STATUS_IRQ /* Clear interrupt priority bits. */
2.15 and $t3, $t3, $t4
2.16 + ori $t3, $t3, (3 << STATUS_IRQ_SHIFT)
2.17 li $t4, ~STATUS_BEV /* CP0_STATUS &= ~STATUS_BEV (use non-bootloader vectors) */
2.18 and $t3, $t3, $t4
2.19 ori $t3, $t3, STATUS_IE
2.20 @@ -937,6 +936,25 @@
2.21 li $v1, (1 << 4) /* DCH0ECON<4> = SIRQEN = 1 */
2.22 sw $v1, SET($v0)
2.23
2.24 + /*
2.25 + Suspend delivery of the timer interrupt during the visible period.
2.26 + The condition still occurs, however.
2.27 + */
2.28 +
2.29 + la $v0, IEC0
2.30 + li $v1, (1 << 9)
2.31 + sw $v1, CLR($v0) /* T2IE = 0 */
2.32 +
2.33 + la $v0, IPC2
2.34 + li $v1, 0b11111
2.35 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
2.36 + li $v1, 0b00111
2.37 + sw $v1, SET($v0) /* T2IP = 1; T2IS = 3 */
2.38 +
2.39 + la $v0, IEC0
2.40 + li $v1, (1 << 9)
2.41 + sw $v1, SET($v0) /* T2IE = 0 */
2.42 +
2.43 _vbp_active_ret:
2.44 jr $ra
2.45 nop
2.46 @@ -956,6 +974,22 @@
2.47
2.48 la $s1, vfp_active
2.49
2.50 + /* Restore delivery of the timer interrupt after the visible period. */
2.51 +
2.52 + la $v0, IEC0
2.53 + li $v1, (1 << 9)
2.54 + sw $v1, CLR($v0) /* T2IE = 0 */
2.55 +
2.56 + la $v0, IPC2
2.57 + li $v1, 0b11111
2.58 + sw $v1, CLR($v0) /* T2IP, T2IS = 0 */
2.59 + li $v1, 0b11111
2.60 + sw $v1, SET($v0) /* T2IP = 7; T2IS = 3 */
2.61 +
2.62 + la $v0, IEC0
2.63 + li $v1, (1 << 9)
2.64 + sw $v1, SET($v0) /* T2IE = 1 */
2.65 +
2.66 _visible_active_ret:
2.67 jr $ra
2.68 nop