1.1 --- a/vga.S Fri Nov 03 01:20:19 2017 +0100
1.2 +++ b/vga.S Fri Nov 03 23:25:06 2017 +0100
1.3 @@ -720,7 +720,6 @@
1.4
1.5 /* Clear the timer interrupt condition. */
1.6
1.7 - li $v1, (1 << 9) /* IFS0<9> = T2IF = 0 */
1.8 sw $v1, CLR($v0)
1.9
1.10 /*
1.11 @@ -759,7 +758,6 @@
1.12
1.13 /* Clear the DMA interrupt condition. */
1.14
1.15 - li $v1, (1 << 28) /* IFS1<28> = DMA0IF = 0 */
1.16 sw $v1, CLR($v0)
1.17
1.18 /* Test the block transfer completion interrupt flag. */
1.19 @@ -772,7 +770,6 @@
1.20
1.21 /* Clear the block transfer completion interrupt flag. */
1.22
1.23 - li $v1, (1 << 3) /* CHBCIF = 0 */
1.24 sw $v1, CLR($v0)
1.25
1.26 /*
1.27 @@ -918,12 +915,6 @@
1.28
1.29 la $s1, vfp_active
1.30
1.31 - /* Clear the timer interrupt condition. */
1.32 -
1.33 - la $v0, IFS0
1.34 - li $v1, (1 << 9) /* IFS0<9> = T2IF = 0 */
1.35 - sw $v1, CLR($v0)
1.36 -
1.37 /* Re-enable the timer interrupt after the visible period. */
1.38
1.39 la $v0, IEC0
1.40 @@ -983,22 +974,11 @@
1.41
1.42 _visible_dma_update:
1.43
1.44 - /* Disable line channel. */
1.45 -
1.46 - la $v0, DCH0CON
1.47 - li $v1, 0b10000000
1.48 - sw $v1, CLR($v0)
1.49 -
1.50 /* Update the source address. */
1.51
1.52 la $v0, DCH0SSA
1.53 sw $s2, 0($v0)
1.54
1.55 - /* Enable line channel. */
1.56 -
1.57 - la $v0, DCH0CON
1.58 - sw $v1, SET($v0)
1.59 -
1.60 _visible_update_ret:
1.61 j irq_exit
1.62 nop