1.1 --- a/vga.S Fri Sep 29 22:10:11 2017 +0200
1.2 +++ b/vga.S Fri Nov 03 00:40:16 2017 +0100
1.3 @@ -262,7 +262,7 @@
1.4
1.5 init_timer2:
1.6
1.7 - /* Initialise Timer2 interrupt. */
1.8 + /* Initialise Timer2 for sync pulses. */
1.9
1.10 la $v0, T2CON
1.11 sw $zero, 0($v0) /* T2CON = 0 */
1.12 @@ -312,7 +312,7 @@
1.13 data has been transferred using DMA, but this is achieved by just choosing
1.14 suitable start and end values.
1.15
1.16 -Using OC2, Timer 2 triggers a level shifting event and OC2 is reconfigured to
1.17 +Using OC2, Timer2 triggers a level shifting event and OC2 is reconfigured to
1.18 reverse the level at a later point. In this way, the vsync pulse is generated
1.19 and is synchronised to the display lines.
1.20 */
1.21 @@ -511,7 +511,7 @@
1.22
1.23 /*
1.24 The reset channel has a cell size of a single zero byte:
1.25 - DCHxCSIZ<15:0> = CHCSIZ<15:0> = LINE_LENGTH
1.26 + DCHxCSIZ<15:0> = CHCSIZ<15:0> = 1
1.27 */
1.28
1.29 la $v0, DCH1CSIZ
1.30 @@ -520,7 +520,7 @@
1.31
1.32 /*
1.33 The source has a size identical to the cell size:
1.34 - DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH
1.35 + DCHxSSIZ<15:0> = CHSSIZ<15:0> = LINE_LENGTH or 1
1.36 */
1.37
1.38 la $v0, DCH0SSIZ