1.1 --- a/README.txt Fri Nov 03 23:25:06 2017 +0100
1.2 +++ b/README.txt Sat Nov 04 17:07:15 2017 +0100
1.3 @@ -39,7 +39,7 @@
1.4 D3/RB3 7 22 RB11/PGEC2
1.5 8 21 RB10/PGEC3
1.6 RA2 9 20
1.7 - RA3 10 19
1.8 + CLKO/RA3 10 19
1.9 D4/RB4 11 18 RB9
1.10 12 17 RB8
1.11 13 16 RB7/D7
1.12 @@ -47,6 +47,26 @@
1.13
1.14 Note that RB6 is not available on pin 15 on this device.
1.15
1.16 +Clock Output Routing
1.17 +--------------------
1.18 +
1.19 +CLKO is used to drive a 74HC273 flip-flop clock pulse (CP) input, with the
1.20 +data signals then routed through the flip-flop as follows:
1.21 +
1.22 + MR# 1 \/ 20 VCC
1.23 + out D0/Q0 2 19 Q7/D7 out
1.24 + in D0/D0 3 18 D7/D7 in
1.25 + in D1/D1 4 17 D6
1.26 + out D1/Q1 5 16 Q6
1.27 + out D2/Q2 6 15 Q5/D5 out
1.28 + in D2/D2 7 14 D5/D5 in
1.29 + in D3/D3 8 13 D4/D4 in
1.30 + out D3/Q3 9 12 Q4/D4 out
1.31 + GND 10 11 CP/CLKO in
1.32 +
1.33 +MR# is kept at a high level. All out signals are then supplied to the
1.34 +analogue circuit provided below.
1.35 +
1.36 Data Signal Routing
1.37 -------------------
1.38
2.1 --- a/vga.S Fri Nov 03 23:25:06 2017 +0100
2.2 +++ b/vga.S Sat Nov 04 17:07:15 2017 +0100
2.3 @@ -32,12 +32,16 @@
2.4
2.5 The watchdog timer (FWDTEN) is also disabled.
2.6
2.7 +The primary oscillator is configured to provide an external clock and CLKO
2.8 +output is enabled.
2.9 +
2.10 The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
2.11 RPB4.
2.12 */
2.13
2.14 .section .devcfg1, "a"
2.15 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
2.16 +.word 0xff7fd8d9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
2.17 + DEVCFG1<10> = OSCIOFNC = 0; DEVCFG1<9:8> = POSCMOD<1:0> = 00;
2.18 DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
2.19
2.20 /*
2.21 @@ -115,7 +119,7 @@
2.22 li $t1, (1 << 3) /* PORTA<3> = RA3 */
2.23 sw $t1, CLR($t0)
2.24
2.25 - jal init_oc_pins
2.26 + jal init_io_pins
2.27 nop
2.28
2.29 /* Initialise the status register. */
2.30 @@ -376,7 +380,9 @@
2.31 jr $ra
2.32 nop
2.33
2.34 -init_oc_pins:
2.35 +
2.36 +
2.37 +init_io_pins:
2.38 /* Unlock the configuration register bits. */
2.39
2.40 la $v0, SYSKEY
2.41 @@ -403,6 +409,14 @@
2.42 li $v1, 0b0101 /* RPA1R<3:0> = 0101 (OC2) */
2.43 sw $v1, 0($v0)
2.44
2.45 + /* Map REFCLKO to RPA2. */
2.46 +
2.47 + la $v0, RPA2R
2.48 + li $v1, 0b0111 /* RPA2R<3:0> = 0111 (REFCLKO) */
2.49 + sw $v1, 0($v0)
2.50 +
2.51 + /* Restore CFGCON. */
2.52 +
2.53 la $v0, CFGCON
2.54 sw $t8, 0($v0)
2.55