1.1 --- a/vga.S Fri Nov 03 23:25:06 2017 +0100
1.2 +++ b/vga.S Mon Nov 06 14:37:28 2017 +0100
1.3 @@ -133,7 +133,7 @@
1.4
1.5 /* Initialise timer. */
1.6
1.7 - jal init_timer2
1.8 + jal init_timers
1.9 nop
1.10
1.11 /* Initialise DMA. */
1.12 @@ -260,7 +260,7 @@
1.13
1.14 /* Initialisation routines. */
1.15
1.16 -init_timer2:
1.17 +init_timers:
1.18
1.19 /* Initialise Timer2 for sync pulses. */
1.20
1.21 @@ -299,6 +299,25 @@
1.22 li $v1, (1 << 15)
1.23 sw $v1, SET($v0) /* ON = 1 */
1.24
1.25 + /* Initialise Timer3 for reset DMA cell transfer. */
1.26 +
1.27 + la $v0, T3CON
1.28 + sw $zero, 0($v0) /* T3CON = 0 */
1.29 + nop
1.30 +
1.31 + la $v0, TMR3
1.32 + sw $zero, 0($v0) /* TMR3 = 0 */
1.33 +
1.34 + la $v0, PR3
1.35 + li $v1, 1
1.36 + sw $v1, 0($v0) /* PR3 = 1 */
1.37 +
1.38 + /* Start timer. */
1.39 +
1.40 + la $v0, T3CON
1.41 + li $v1, (1 << 15)
1.42 + sw $v1, SET($v0) /* ON = 1 */
1.43 +
1.44 jr $ra
1.45 nop
1.46
1.47 @@ -492,12 +511,12 @@
1.48
1.49 /*
1.50 Initiate reset channel transfer when channel 0 is finished:
1.51 - DCHxECON<15:8> = CHSIRQ<7:0> = channel 0 interrupt
1.52 + DCHxECON<15:8> = CHSIRQ<7:0> = timer 3 interrupt
1.53 DCHxECON<4> = SIRQEN = 1
1.54 */
1.55
1.56 la $v0, DCH1ECON
1.57 - li $v1, (60 << 8) | (1 << 4)
1.58 + li $v1, (14 << 8) | (1 << 4)
1.59 sw $v1, 0($v0)
1.60
1.61 /*