paul@0 | 1 | /* |
paul@0 | 2 | * Ben NanoNote and Arduino USB Host shield communication. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright 2013 Paul Boddie |
paul@0 | 5 | * |
paul@0 | 6 | * SPI functions derived from those in lib/atben.c by Werner Almesberger: |
paul@0 | 7 | * |
paul@0 | 8 | * Copyright 2010-2011 Werner Almesberger |
paul@0 | 9 | * |
paul@0 | 10 | * This program is free software; you can redistribute it and/or modify |
paul@0 | 11 | * it under the terms of the GNU General Public License as published by |
paul@0 | 12 | * the Free Software Foundation; either version 2 of the License, or |
paul@0 | 13 | * (at your option) any later version. |
paul@0 | 14 | */ |
paul@0 | 15 | |
paul@0 | 16 | #include <ubb/ubb.h> |
paul@0 | 17 | #include <stdio.h> |
paul@8 | 18 | #include <signal.h> |
paul@8 | 19 | #include <stdlib.h> |
paul@13 | 20 | #include <usb.h> |
paul@13 | 21 | |
paul@13 | 22 | /* Found in Python's asdl.h. */ |
paul@13 | 23 | |
paul@13 | 24 | #ifndef __cplusplus |
paul@13 | 25 | typedef enum {false, true} bool; |
paul@13 | 26 | #endif |
paul@0 | 27 | |
paul@0 | 28 | /* Pin assignments: |
paul@0 | 29 | * |
paul@0 | 30 | * Sniffer UBB Shield |
paul@0 | 31 | * ------- ---- ------ |
paul@0 | 32 | * DAT2 DAT2 9 (INT) |
paul@0 | 33 | * CD DAT3 10 (SS) |
paul@0 | 34 | * CMD CMD 7 (RESET) |
paul@0 | 35 | * VCC VDD VIN |
paul@0 | 36 | * CLK CLK 13 (SCLK) |
paul@0 | 37 | * GND GND GND |
paul@0 | 38 | * DAT0 DAT0 11 (MOSI) |
paul@0 | 39 | * DAT1 DAT1 12 (MISO) |
paul@0 | 40 | * 8 (GPX) (not assigned) |
paul@0 | 41 | */ |
paul@0 | 42 | |
paul@0 | 43 | #define MAX_RESET UBB_CMD |
paul@0 | 44 | #define MAX_SCLK UBB_CLK |
paul@0 | 45 | #define MAX_MOSI UBB_DAT0 |
paul@0 | 46 | #define MAX_MISO UBB_DAT1 |
paul@0 | 47 | #define MAX_INT UBB_DAT2 |
paul@0 | 48 | #define MAX_SS UBB_DAT3 |
paul@0 | 49 | |
paul@0 | 50 | /* MAX3421E definitions. */ |
paul@0 | 51 | |
paul@0 | 52 | #define MAX_REG_READ 0x00 |
paul@0 | 53 | #define MAX_REG_WRITE 0x02 |
paul@0 | 54 | |
paul@13 | 55 | #define MAX_REG_RCVFIFO 1 |
paul@13 | 56 | #define MAX_REG_SNDFIFO 2 |
paul@13 | 57 | #define MAX_REG_SUDFIFO 4 |
paul@13 | 58 | #define MAX_REG_RCVBC 6 |
paul@13 | 59 | #define MAX_REG_SNDBC 7 |
paul@4 | 60 | #define MAX_REG_USBIRQ 13 |
paul@7 | 61 | #define MAX_REG_USBIEN 14 |
paul@0 | 62 | #define MAX_REG_USBCTL 15 |
paul@7 | 63 | #define MAX_REG_CPUCTL 16 |
paul@0 | 64 | #define MAX_REG_PINCTL 17 |
paul@0 | 65 | #define MAX_REG_REVISION 18 |
paul@7 | 66 | #define MAX_REG_HIRQ 25 |
paul@7 | 67 | #define MAX_REG_HIEN 26 |
paul@0 | 68 | #define MAX_REG_MODE 27 |
paul@13 | 69 | #define MAX_REG_PERADDR 28 |
paul@7 | 70 | #define MAX_REG_HCTL 29 |
paul@13 | 71 | #define MAX_REG_HXFR 30 |
paul@0 | 72 | #define MAX_REG_HRSL 31 |
paul@0 | 73 | |
paul@4 | 74 | #define MAX_USBIRQ_OSCOKIRQ 1 |
paul@4 | 75 | #define MAX_USBIRQ_NOVBUSIRQ 32 |
paul@4 | 76 | #define MAX_USBIRQ_VBUSIRQ 64 |
paul@4 | 77 | |
paul@0 | 78 | #define MAX_USBCTL_PWRDOWN 16 |
paul@0 | 79 | #define MAX_USBCTL_CHIPRES 32 |
paul@0 | 80 | |
paul@7 | 81 | #define MAX_CPUCTL_IE 1 |
paul@7 | 82 | |
paul@0 | 83 | #define MAX_PINCTL_POSINT_LOW 0 |
paul@0 | 84 | #define MAX_PINCTL_POSINT_HIGH 4 |
paul@0 | 85 | #define MAX_PINCTL_INTLEVEL_EDGE 0 |
paul@0 | 86 | #define MAX_PINCTL_INTLEVEL_LEVEL 8 |
paul@0 | 87 | #define MAX_PINCTL_FDUPSPI_HALF 0 |
paul@0 | 88 | #define MAX_PINCTL_FDUPSPI_FULL 16 |
paul@0 | 89 | |
paul@7 | 90 | #define MAX_HIRQ_BUSEVENTIRQ 1 |
paul@7 | 91 | #define MAX_HIRQ_RWUIRQ 2 |
paul@7 | 92 | #define MAX_HIRQ_RCVDAVIRQ 4 |
paul@7 | 93 | #define MAX_HIRQ_SNDBAVIRQ 8 |
paul@7 | 94 | #define MAX_HIRQ_SUSDNIRQ 16 |
paul@7 | 95 | #define MAX_HIRQ_CONDETIRQ 32 |
paul@7 | 96 | #define MAX_HIRQ_FRAMEIRQ 64 |
paul@7 | 97 | #define MAX_HIRQ_HXFRDNIRQ 128 |
paul@7 | 98 | |
paul@7 | 99 | #define MAX_HIEN_CONDETIE 32 |
paul@7 | 100 | |
paul@0 | 101 | #define MAX_MODE_PERIPHERAL 0 |
paul@0 | 102 | #define MAX_MODE_HOST 1 |
paul@7 | 103 | #define MAX_MODE_LOWSPEED 2 |
paul@7 | 104 | #define MAX_MODE_SOFKAENAB 8 |
paul@0 | 105 | #define MAX_MODE_SEPIRQ_OFF 0 |
paul@0 | 106 | #define MAX_MODE_SEPIRQ_ON 16 |
paul@0 | 107 | #define MAX_MODE_DMPULLDN 64 |
paul@0 | 108 | #define MAX_MODE_DPPULLDN 128 |
paul@0 | 109 | |
paul@12 | 110 | #define MAX_MODE_HOST_ENABLED MAX_MODE_HOST | MAX_MODE_SEPIRQ_OFF | MAX_MODE_DMPULLDN | MAX_MODE_DPPULLDN |
paul@12 | 111 | #define MAX_MODE_HOST_FULLSPEED MAX_MODE_HOST_ENABLED |
paul@12 | 112 | #define MAX_MODE_HOST_LOWSPEED MAX_MODE_HOST_ENABLED | MAX_MODE_LOWSPEED |
paul@12 | 113 | |
paul@7 | 114 | #define MAX_HCTL_SAMPLEBUS 4 |
paul@13 | 115 | #define MAX_HCTL_RCVTOG0 16 |
paul@13 | 116 | #define MAX_HCTL_RCVTOG1 32 |
paul@13 | 117 | #define MAX_HCTL_SNDTOG0 64 |
paul@13 | 118 | #define MAX_HCTL_SNDTOG1 128 |
paul@13 | 119 | |
paul@13 | 120 | #define MAX_HXFR_SETUP 16 |
paul@13 | 121 | #define MAX_HXFR_OUTNIN 32 |
paul@13 | 122 | #define MAX_HXFR_HS 128 |
paul@7 | 123 | |
paul@7 | 124 | #define MAX_HRSL_JSTATUS 128 |
paul@7 | 125 | #define MAX_HRSL_KSTATUS 64 |
paul@13 | 126 | #define MAX_HRSL_SNDTOGRD 32 |
paul@13 | 127 | #define MAX_HRSL_RCVTOGRD 16 |
paul@13 | 128 | #define MAX_HRSL_HRSLT 15 |
paul@7 | 129 | |
paul@0 | 130 | #define max_reg(n) ((uint8_t) (n << 3)) |
paul@0 | 131 | #define max_reg_read(n) (max_reg(n) | MAX_REG_READ) |
paul@0 | 132 | #define max_reg_write(n) (max_reg(n) | MAX_REG_WRITE) |
paul@0 | 133 | |
paul@0 | 134 | void spi_begin() |
paul@0 | 135 | { |
paul@0 | 136 | CLR(MAX_SS); |
paul@0 | 137 | } |
paul@0 | 138 | |
paul@0 | 139 | void spi_end() |
paul@0 | 140 | { |
paul@0 | 141 | SET(MAX_SS); |
paul@0 | 142 | } |
paul@0 | 143 | |
paul@0 | 144 | /** |
paul@0 | 145 | * Send the given value via MOSI while receiving a value via MISO. |
paul@0 | 146 | * This requires full-duplex SPI and will produce a status value for the first |
paul@0 | 147 | * value sent (the command). |
paul@0 | 148 | */ |
paul@0 | 149 | uint8_t spi_sendrecv(uint8_t v) |
paul@0 | 150 | { |
paul@0 | 151 | uint8_t result = 0; |
paul@0 | 152 | uint8_t mask; |
paul@0 | 153 | |
paul@0 | 154 | for (mask = 0x80; mask; mask >>= 1) |
paul@0 | 155 | { |
paul@0 | 156 | if (v & mask) |
paul@0 | 157 | { |
paul@7 | 158 | #ifdef DEBUG |
paul@0 | 159 | printf("1"); |
paul@7 | 160 | #endif |
paul@0 | 161 | SET(MAX_MOSI); |
paul@0 | 162 | } |
paul@0 | 163 | else |
paul@0 | 164 | { |
paul@7 | 165 | #ifdef DEBUG |
paul@0 | 166 | printf("0"); |
paul@7 | 167 | #endif |
paul@0 | 168 | CLR(MAX_MOSI); |
paul@0 | 169 | } |
paul@0 | 170 | |
paul@0 | 171 | /* Wait for stable output signal. */ |
paul@0 | 172 | |
paul@0 | 173 | SET(MAX_SCLK); |
paul@0 | 174 | |
paul@0 | 175 | if (PIN(MAX_MISO)) |
paul@0 | 176 | result |= mask; |
paul@0 | 177 | |
paul@0 | 178 | CLR(MAX_SCLK); |
paul@0 | 179 | } |
paul@0 | 180 | |
paul@7 | 181 | #ifdef DEBUG |
paul@0 | 182 | printf("\n"); |
paul@7 | 183 | #endif |
paul@0 | 184 | return result; |
paul@0 | 185 | } |
paul@0 | 186 | |
paul@6 | 187 | uint8_t max_read(uint8_t reg, uint8_t *status) |
paul@6 | 188 | { |
paul@6 | 189 | uint8_t result = 0, tmpstatus = 0; |
paul@6 | 190 | |
paul@6 | 191 | tmpstatus = 0; |
paul@6 | 192 | |
paul@6 | 193 | spi_begin(); |
paul@6 | 194 | tmpstatus = spi_sendrecv(max_reg_read(reg)); |
paul@6 | 195 | result = spi_sendrecv(0); |
paul@6 | 196 | spi_end(); |
paul@6 | 197 | |
paul@6 | 198 | if (status != NULL) |
paul@6 | 199 | *status = tmpstatus; |
paul@6 | 200 | |
paul@6 | 201 | return result; |
paul@6 | 202 | } |
paul@6 | 203 | |
paul@6 | 204 | uint8_t max_write(uint8_t reg, uint8_t value) |
paul@6 | 205 | { |
paul@6 | 206 | uint8_t status = 0; |
paul@6 | 207 | |
paul@6 | 208 | spi_begin(); |
paul@6 | 209 | status = spi_sendrecv(max_reg_write(reg)); |
paul@6 | 210 | spi_sendrecv(value); |
paul@6 | 211 | spi_end(); |
paul@6 | 212 | |
paul@6 | 213 | return status; |
paul@6 | 214 | } |
paul@6 | 215 | |
paul@13 | 216 | /** |
paul@13 | 217 | * Return whether data can be sent. |
paul@13 | 218 | */ |
paul@13 | 219 | bool max_can_send() |
paul@13 | 220 | { |
paul@13 | 221 | uint8_t status = max_read(MAX_REG_HIRQ, NULL); |
paul@13 | 222 | |
paul@13 | 223 | return !(status & MAX_HIRQ_SNDBAVIRQ); |
paul@13 | 224 | } |
paul@13 | 225 | |
paul@13 | 226 | /** |
paul@13 | 227 | * Set the sending data toggle. |
paul@13 | 228 | */ |
paul@13 | 229 | void max_set_send_toggle(bool toggle) |
paul@13 | 230 | { |
paul@13 | 231 | max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_SNDTOG1 : MAX_HCTL_SNDTOG0); |
paul@13 | 232 | } |
paul@13 | 233 | |
paul@13 | 234 | /** |
paul@13 | 235 | * Return the sending data toggle. |
paul@13 | 236 | */ |
paul@13 | 237 | bool max_get_send_toggle() |
paul@13 | 238 | { |
paul@13 | 239 | return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_SNDTOGRD) != 0; |
paul@13 | 240 | } |
paul@13 | 241 | |
paul@13 | 242 | /** |
paul@13 | 243 | * Set the receiving data toggle. |
paul@13 | 244 | */ |
paul@13 | 245 | void max_set_recv_toggle(bool toggle) |
paul@13 | 246 | { |
paul@13 | 247 | max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_RCVTOG1 : MAX_HCTL_RCVTOG0); |
paul@13 | 248 | } |
paul@13 | 249 | |
paul@13 | 250 | /** |
paul@13 | 251 | * Return the receiving data toggle. |
paul@13 | 252 | */ |
paul@13 | 253 | bool max_get_recv_toggle() |
paul@13 | 254 | { |
paul@13 | 255 | return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_RCVTOGRD) != 0; |
paul@13 | 256 | } |
paul@13 | 257 | |
paul@13 | 258 | /** |
paul@13 | 259 | * Wait for handshake/timeout after a transfer. |
paul@13 | 260 | */ |
paul@13 | 261 | uint8_t max_wait_transfer(uint8_t status) |
paul@13 | 262 | { |
paul@13 | 263 | while (!(status & MAX_HIRQ_HXFRDNIRQ)) |
paul@13 | 264 | { |
paul@13 | 265 | status = max_read(MAX_REG_HIRQ, NULL); |
paul@13 | 266 | } |
paul@13 | 267 | |
paul@13 | 268 | return status; |
paul@13 | 269 | } |
paul@13 | 270 | |
paul@13 | 271 | /** |
paul@13 | 272 | * Send HS payload for control transfers. |
paul@13 | 273 | */ |
paul@13 | 274 | uint8_t max_send_hs() |
paul@13 | 275 | { |
paul@13 | 276 | uint8_t status = max_write(MAX_REG_HXFR, MAX_HXFR_HS); |
paul@13 | 277 | return max_wait_transfer(status); |
paul@13 | 278 | } |
paul@13 | 279 | |
paul@13 | 280 | /** |
paul@13 | 281 | * Write the given data to the FIFO. |
paul@13 | 282 | */ |
paul@13 | 283 | void max_write_fifo(uint8_t endpoint, uint8_t *data, uint8_t len) |
paul@13 | 284 | { |
paul@13 | 285 | uint8_t count; |
paul@13 | 286 | |
paul@13 | 287 | for (count = 0; count < len; count++) |
paul@13 | 288 | { |
paul@13 | 289 | max_write(endpoint ? MAX_REG_SNDFIFO : MAX_REG_SUDFIFO, data[count]); |
paul@13 | 290 | } |
paul@13 | 291 | |
paul@13 | 292 | if (endpoint) |
paul@13 | 293 | max_write(MAX_REG_SNDBC, len); |
paul@13 | 294 | } |
paul@13 | 295 | |
paul@13 | 296 | /** |
paul@13 | 297 | * Read the data from the FIFO. |
paul@13 | 298 | */ |
paul@13 | 299 | void max_read_fifo(uint8_t *data, uint8_t *len, uint8_t *datalimit) |
paul@13 | 300 | { |
paul@13 | 301 | uint8_t count, received = max_read(MAX_REG_RCVBC, NULL); |
paul@13 | 302 | |
paul@13 | 303 | *len += received; |
paul@13 | 304 | |
paul@13 | 305 | for (count = 0; (count < received) && (data < datalimit); count++) |
paul@13 | 306 | { |
paul@13 | 307 | *data++ = max_read(MAX_REG_RCVFIFO, NULL); |
paul@13 | 308 | } |
paul@13 | 309 | } |
paul@13 | 310 | |
paul@13 | 311 | /** |
paul@13 | 312 | * Send a request to the given address and endpoint, using the supplied data |
paul@13 | 313 | * payload with the given length, indicating the preserved toggle state of the |
paul@13 | 314 | * endpoint (which will be updated). |
paul@13 | 315 | */ |
paul@13 | 316 | uint8_t max_send(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t len, bool *toggle) |
paul@13 | 317 | { |
paul@13 | 318 | uint8_t status, hrsl = 0; |
paul@13 | 319 | |
paul@13 | 320 | max_write_fifo(endpoint, data, len); |
paul@13 | 321 | |
paul@13 | 322 | max_set_send_toggle(*toggle); |
paul@13 | 323 | |
paul@13 | 324 | /* Set the address. */ |
paul@13 | 325 | |
paul@13 | 326 | max_write(MAX_REG_PERADDR, address); |
paul@13 | 327 | |
paul@13 | 328 | /* Initiate the transfer. */ |
paul@13 | 329 | |
paul@13 | 330 | do |
paul@13 | 331 | { |
paul@13 | 332 | status = max_write(MAX_REG_HXFR, endpoint | MAX_HXFR_OUTNIN | (endpoint ? 0 : MAX_HXFR_SETUP)); |
paul@13 | 333 | status = max_wait_transfer(status); |
paul@13 | 334 | |
paul@13 | 335 | /* Test for usable data. */ |
paul@13 | 336 | |
paul@13 | 337 | if (!(status & MAX_HIRQ_SNDBAVIRQ)) |
paul@13 | 338 | continue; |
paul@13 | 339 | |
paul@13 | 340 | hrsl = max_read(MAX_REG_HRSL, &status); |
paul@13 | 341 | } |
paul@13 | 342 | while ((hrsl & MAX_HRSL_HRSLT) != 0); |
paul@13 | 343 | |
paul@13 | 344 | *toggle = max_get_send_toggle(); |
paul@13 | 345 | |
paul@13 | 346 | return status; |
paul@13 | 347 | } |
paul@13 | 348 | |
paul@13 | 349 | /** |
paul@13 | 350 | * Make a request for data from the given address and endpoint, collecting it in |
paul@13 | 351 | * the supplied buffer with the given length, indicating the preserved toggle |
paul@13 | 352 | * state of the endpoint (which will be updated), and providing optional setup |
paul@13 | 353 | * data (for control transfers). The length will be updated to indicate the |
paul@13 | 354 | * total length of the received data. |
paul@13 | 355 | */ |
paul@13 | 356 | uint8_t max_recv(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t *len, bool *toggle, uint8_t *setup) |
paul@13 | 357 | { |
paul@13 | 358 | uint8_t *datalimit = data + *len; |
paul@13 | 359 | uint8_t status, hrsl = 0; |
paul@13 | 360 | |
paul@13 | 361 | /* Write control transfer information, if appropriate. */ |
paul@13 | 362 | |
paul@13 | 363 | if (!endpoint) |
paul@13 | 364 | max_write_fifo(endpoint, setup, 8); |
paul@13 | 365 | |
paul@13 | 366 | max_set_send_toggle(*toggle); |
paul@13 | 367 | |
paul@13 | 368 | /* Set the address. */ |
paul@13 | 369 | |
paul@13 | 370 | max_write(MAX_REG_PERADDR, address); |
paul@13 | 371 | |
paul@13 | 372 | /* Initiate the transfer. */ |
paul@13 | 373 | |
paul@13 | 374 | do |
paul@13 | 375 | { |
paul@13 | 376 | status = max_write(MAX_REG_HXFR, endpoint); |
paul@13 | 377 | status = max_wait_transfer(status); |
paul@13 | 378 | |
paul@13 | 379 | /* Test for usable data. */ |
paul@13 | 380 | |
paul@13 | 381 | if (!(status & MAX_HIRQ_RCVDAVIRQ)) |
paul@13 | 382 | continue; |
paul@13 | 383 | |
paul@13 | 384 | hrsl = max_read(MAX_REG_HRSL, &status); |
paul@13 | 385 | } |
paul@13 | 386 | while ((hrsl & MAX_HRSL_HRSLT) != 0); |
paul@13 | 387 | |
paul@13 | 388 | do |
paul@13 | 389 | { |
paul@13 | 390 | max_read_fifo(data, len, datalimit); |
paul@13 | 391 | |
paul@13 | 392 | /* Indicate that all data has been read. */ |
paul@13 | 393 | |
paul@13 | 394 | status = max_write(MAX_REG_HIRQ, MAX_HIRQ_RCVDAVIRQ); |
paul@13 | 395 | } |
paul@13 | 396 | while (status & MAX_HIRQ_RCVDAVIRQ); |
paul@13 | 397 | |
paul@13 | 398 | *toggle = max_get_send_toggle(); |
paul@13 | 399 | |
paul@13 | 400 | return status; |
paul@13 | 401 | } |
paul@13 | 402 | |
paul@3 | 403 | void chipreset() |
paul@3 | 404 | { |
paul@3 | 405 | printf("Resetting...\n"); |
paul@6 | 406 | max_write(MAX_REG_USBCTL, MAX_USBCTL_CHIPRES); |
paul@3 | 407 | |
paul@3 | 408 | printf("Clearing the reset...\n"); |
paul@6 | 409 | max_write(MAX_REG_USBCTL, 0); |
paul@3 | 410 | } |
paul@3 | 411 | |
paul@4 | 412 | uint8_t check() |
paul@4 | 413 | { |
paul@6 | 414 | uint8_t oscillator; |
paul@4 | 415 | |
paul@6 | 416 | oscillator = max_read(MAX_REG_USBIRQ, NULL); |
paul@4 | 417 | |
paul@4 | 418 | return (oscillator & ~(MAX_USBIRQ_NOVBUSIRQ | MAX_USBIRQ_VBUSIRQ)) == MAX_USBIRQ_OSCOKIRQ; |
paul@4 | 419 | } |
paul@4 | 420 | |
paul@7 | 421 | uint8_t wait() |
paul@7 | 422 | { |
paul@7 | 423 | uint16_t timeout = 1024; |
paul@7 | 424 | |
paul@7 | 425 | /* Wait for the oscillator before performing USB activity. */ |
paul@7 | 426 | |
paul@7 | 427 | printf("Waiting...\n"); |
paul@7 | 428 | |
paul@7 | 429 | while ((timeout > 0) && (!check())) |
paul@7 | 430 | { |
paul@7 | 431 | timeout--; |
paul@7 | 432 | } |
paul@7 | 433 | |
paul@7 | 434 | printf("Iterations remaining: %d\n", timeout); |
paul@7 | 435 | |
paul@7 | 436 | return timeout; |
paul@7 | 437 | } |
paul@7 | 438 | |
paul@11 | 439 | uint8_t samplebusready() |
paul@7 | 440 | { |
paul@7 | 441 | uint8_t result; |
paul@7 | 442 | |
paul@7 | 443 | result = max_read(MAX_REG_HCTL, NULL); |
paul@7 | 444 | |
paul@7 | 445 | return !(result & MAX_HCTL_SAMPLEBUS); |
paul@7 | 446 | } |
paul@7 | 447 | |
paul@11 | 448 | void samplebus() |
paul@11 | 449 | { |
paul@11 | 450 | max_write(MAX_REG_HCTL, MAX_HCTL_SAMPLEBUS); |
paul@11 | 451 | while (!samplebusready()); |
paul@11 | 452 | } |
paul@11 | 453 | |
paul@13 | 454 | /** |
paul@13 | 455 | * Handle the connection or disconnection of a device, returning true if the |
paul@13 | 456 | * device is now connected or false otherwise. |
paul@13 | 457 | */ |
paul@13 | 458 | bool devicechanged() |
paul@11 | 459 | { |
paul@11 | 460 | uint8_t hrsl, mode; |
paul@11 | 461 | |
paul@11 | 462 | hrsl = max_read(MAX_REG_HRSL, NULL); |
paul@11 | 463 | mode = max_read(MAX_REG_MODE, NULL); |
paul@11 | 464 | |
paul@11 | 465 | if ((hrsl & MAX_HRSL_JSTATUS) && (hrsl & MAX_HRSL_KSTATUS)) |
paul@11 | 466 | { |
paul@11 | 467 | printf("Bad device status.\n"); |
paul@11 | 468 | } |
paul@11 | 469 | else if (!(hrsl & MAX_HRSL_JSTATUS) && !(hrsl & MAX_HRSL_KSTATUS)) |
paul@11 | 470 | { |
paul@11 | 471 | printf("Device disconnected.\n"); |
paul@11 | 472 | } |
paul@11 | 473 | else |
paul@11 | 474 | { |
paul@11 | 475 | printf("Device connected.\n"); |
paul@11 | 476 | |
paul@11 | 477 | /* Low speed device when J and lowspeed have the same level. |
paul@11 | 478 | Since J and K should have opposing levels, K can be tested when |
paul@11 | 479 | lowspeed is low. */ |
paul@11 | 480 | |
paul@11 | 481 | if (((hrsl & MAX_HRSL_JSTATUS) && (mode & MAX_MODE_LOWSPEED)) || |
paul@11 | 482 | ((hrsl & MAX_HRSL_KSTATUS) && !(mode & MAX_MODE_LOWSPEED))) |
paul@11 | 483 | { |
paul@11 | 484 | printf("Device is low speed.\n"); |
paul@12 | 485 | max_write(MAX_REG_MODE, MAX_MODE_HOST_LOWSPEED); |
paul@11 | 486 | } |
paul@11 | 487 | else |
paul@11 | 488 | { |
paul@11 | 489 | printf("Device is full speed.\n"); |
paul@12 | 490 | max_write(MAX_REG_MODE, MAX_MODE_HOST_FULLSPEED); |
paul@11 | 491 | } |
paul@13 | 492 | |
paul@13 | 493 | return true; |
paul@11 | 494 | } |
paul@13 | 495 | |
paul@13 | 496 | return false; |
paul@13 | 497 | } |
paul@13 | 498 | |
paul@13 | 499 | void setup_packet(uint8_t *setup, uint8_t request_type, uint8_t request, uint16_t value, uint16_t index, uint16_t length) |
paul@13 | 500 | { |
paul@13 | 501 | setup[0] = request_type; |
paul@13 | 502 | setup[1] = request; |
paul@13 | 503 | setup[2] = value & 0xff; |
paul@13 | 504 | setup[3] = value >> 8; |
paul@13 | 505 | setup[4] = index & 0xff; |
paul@13 | 506 | setup[5] = index >> 8; |
paul@13 | 507 | setup[6] = length & 0xff; |
paul@13 | 508 | setup[7] = length >> 8; |
paul@11 | 509 | } |
paul@11 | 510 | |
paul@8 | 511 | void shutdown(int signum) |
paul@8 | 512 | { |
paul@8 | 513 | printf("Closing...\n"); |
paul@8 | 514 | ubb_close(0); |
paul@8 | 515 | exit(1); |
paul@8 | 516 | } |
paul@8 | 517 | |
paul@0 | 518 | int main(int argc, char *argv[]) |
paul@0 | 519 | { |
paul@8 | 520 | uint8_t status = 0, revision = 0; |
paul@7 | 521 | uint16_t count; |
paul@13 | 522 | bool in_toggle = 0; |
paul@13 | 523 | uint8_t data[64], len = 64, setup[8]; |
paul@0 | 524 | |
paul@8 | 525 | signal(SIGINT, &shutdown); |
paul@8 | 526 | |
paul@0 | 527 | if (ubb_open(0) < 0) { |
paul@0 | 528 | perror("ubb_open"); |
paul@0 | 529 | return 1; |
paul@0 | 530 | } |
paul@0 | 531 | |
paul@0 | 532 | ubb_power(1); |
paul@0 | 533 | printf("Power on.\n"); |
paul@0 | 534 | |
paul@0 | 535 | OUT(MAX_SS); |
paul@0 | 536 | OUT(MAX_MOSI); |
paul@0 | 537 | OUT(MAX_SCLK); |
paul@0 | 538 | OUT(MAX_RESET); |
paul@0 | 539 | IN(MAX_INT); |
paul@0 | 540 | IN(MAX_MISO); |
paul@0 | 541 | |
paul@0 | 542 | /* Initialise SPI. */ |
paul@7 | 543 | /* Set SS# to 1. */ |
paul@0 | 544 | |
paul@0 | 545 | SET(MAX_SS); |
paul@0 | 546 | CLR(MAX_MOSI); |
paul@0 | 547 | CLR(MAX_SCLK); |
paul@7 | 548 | SET(MAX_RESET); |
paul@0 | 549 | |
paul@0 | 550 | /* Initialise the MAX3421E. */ |
paul@0 | 551 | |
paul@0 | 552 | /* Set full-duplex, interrupt signalling. */ |
paul@0 | 553 | |
paul@0 | 554 | printf("Setting pin control...\n"); |
paul@6 | 555 | max_write(MAX_REG_PINCTL, MAX_PINCTL_INTLEVEL_LEVEL | MAX_PINCTL_FDUPSPI_FULL); |
paul@0 | 556 | |
paul@3 | 557 | chipreset(); |
paul@7 | 558 | printf("Ready? %d\n", wait()); |
paul@7 | 559 | |
paul@7 | 560 | /* Check various registers. */ |
paul@7 | 561 | |
paul@7 | 562 | printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); |
paul@7 | 563 | printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); |
paul@0 | 564 | |
paul@0 | 565 | /* Set host mode. */ |
paul@0 | 566 | |
paul@0 | 567 | printf("Setting mode...\n"); |
paul@12 | 568 | status = max_write(MAX_REG_MODE, MAX_MODE_HOST_ENABLED); |
paul@7 | 569 | |
paul@7 | 570 | printf("Setting INT signalling...\n"); |
paul@7 | 571 | status = max_write(MAX_REG_CPUCTL, MAX_CPUCTL_IE); |
paul@7 | 572 | |
paul@7 | 573 | printf("Setting connection signalling...\n"); |
paul@7 | 574 | status = max_write(MAX_REG_HIEN, MAX_HIEN_CONDETIE); |
paul@7 | 575 | |
paul@7 | 576 | /* Check various registers. */ |
paul@7 | 577 | |
paul@7 | 578 | printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); |
paul@7 | 579 | printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); |
paul@7 | 580 | printf("IE: %x\n", max_read(MAX_REG_HIEN, &status)); |
paul@7 | 581 | printf("CPU: %x\n", max_read(MAX_REG_CPUCTL, &status)); |
paul@7 | 582 | printf("Pin: %x\n", max_read(MAX_REG_PINCTL, &status)); |
paul@7 | 583 | printf("USBIRQ: %x\n", max_read(MAX_REG_USBIRQ, &status)); |
paul@7 | 584 | printf("USBIE: %x\n", max_read(MAX_REG_USBIEN, &status)); |
paul@0 | 585 | |
paul@0 | 586 | /* Read from the REVISION register. */ |
paul@0 | 587 | |
paul@0 | 588 | printf("Reading...\n"); |
paul@6 | 589 | revision = max_read(MAX_REG_REVISION, &status); |
paul@0 | 590 | printf("Revision = %x\n", revision); |
paul@7 | 591 | |
paul@8 | 592 | for (count = 0; count <= 65535; count++) |
paul@7 | 593 | { |
paul@8 | 594 | if (!PIN(MAX_INT)) |
paul@7 | 595 | { |
paul@9 | 596 | status = max_read(MAX_REG_HIRQ, NULL); |
paul@9 | 597 | |
paul@13 | 598 | if ((status & MAX_HIRQ_CONDETIRQ) && devicechanged() && max_can_send()) |
paul@13 | 599 | { |
paul@13 | 600 | printf("Sending control request to address 0, endpoint 0...\n"); |
paul@13 | 601 | setup_packet(setup, USB_ENDPOINT_IN, USB_REQ_GET_DESCRIPTOR, USB_DT_DEVICE, 0, USB_DT_DEVICE_SIZE); |
paul@13 | 602 | max_recv(0, 0, data, &len, &in_toggle, setup); |
paul@13 | 603 | } |
paul@8 | 604 | if (status & MAX_HIRQ_SUSDNIRQ) |
paul@8 | 605 | printf("Suspend done.\n"); |
paul@8 | 606 | if (status & MAX_HIRQ_BUSEVENTIRQ) |
paul@8 | 607 | printf("Bus event.\n"); |
paul@8 | 608 | if (status & MAX_HIRQ_RCVDAVIRQ) |
paul@8 | 609 | printf("Data received.\n"); |
paul@7 | 610 | |
paul@8 | 611 | max_write(MAX_REG_HIRQ, status); |
paul@7 | 612 | } |
paul@7 | 613 | } |
paul@0 | 614 | |
paul@0 | 615 | printf("Closing...\n"); |
paul@0 | 616 | ubb_close(0); |
paul@0 | 617 | |
paul@0 | 618 | return 0; |
paul@0 | 619 | } |