paul@0 | 1 | /* |
paul@0 | 2 | * Ben NanoNote and Arduino USB Host shield communication. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright 2013 Paul Boddie |
paul@0 | 5 | * |
paul@0 | 6 | * SPI functions derived from those in lib/atben.c by Werner Almesberger: |
paul@0 | 7 | * |
paul@0 | 8 | * Copyright 2010-2011 Werner Almesberger |
paul@0 | 9 | * |
paul@0 | 10 | * This program is free software; you can redistribute it and/or modify |
paul@0 | 11 | * it under the terms of the GNU General Public License as published by |
paul@0 | 12 | * the Free Software Foundation; either version 2 of the License, or |
paul@0 | 13 | * (at your option) any later version. |
paul@0 | 14 | */ |
paul@0 | 15 | |
paul@0 | 16 | #include <ubb/ubb.h> |
paul@0 | 17 | #include <stdio.h> |
paul@8 | 18 | #include <signal.h> |
paul@8 | 19 | #include <stdlib.h> |
paul@13 | 20 | #include <usb.h> |
paul@15 | 21 | #include <unistd.h> |
paul@13 | 22 | |
paul@13 | 23 | /* Found in Python's asdl.h. */ |
paul@13 | 24 | |
paul@13 | 25 | #ifndef __cplusplus |
paul@13 | 26 | typedef enum {false, true} bool; |
paul@13 | 27 | #endif |
paul@0 | 28 | |
paul@15 | 29 | /* Initialisation states. */ |
paul@15 | 30 | |
paul@15 | 31 | typedef enum |
paul@15 | 32 | { |
paul@15 | 33 | MAX_DEVSTATE_INIT = 0, |
paul@15 | 34 | MAX_DEVSTATE_CONNECTED = 1, |
paul@15 | 35 | MAX_DEVSTATE_RESET = 2, |
paul@15 | 36 | MAX_DEVSTATE_READY = 3 |
paul@15 | 37 | } max_devstate; |
paul@15 | 38 | |
paul@0 | 39 | /* Pin assignments: |
paul@0 | 40 | * |
paul@0 | 41 | * Sniffer UBB Shield |
paul@0 | 42 | * ------- ---- ------ |
paul@0 | 43 | * DAT2 DAT2 9 (INT) |
paul@0 | 44 | * CD DAT3 10 (SS) |
paul@0 | 45 | * CMD CMD 7 (RESET) |
paul@0 | 46 | * VCC VDD VIN |
paul@0 | 47 | * CLK CLK 13 (SCLK) |
paul@0 | 48 | * GND GND GND |
paul@0 | 49 | * DAT0 DAT0 11 (MOSI) |
paul@0 | 50 | * DAT1 DAT1 12 (MISO) |
paul@0 | 51 | * 8 (GPX) (not assigned) |
paul@0 | 52 | */ |
paul@0 | 53 | |
paul@0 | 54 | #define MAX_RESET UBB_CMD |
paul@0 | 55 | #define MAX_SCLK UBB_CLK |
paul@0 | 56 | #define MAX_MOSI UBB_DAT0 |
paul@0 | 57 | #define MAX_MISO UBB_DAT1 |
paul@0 | 58 | #define MAX_INT UBB_DAT2 |
paul@0 | 59 | #define MAX_SS UBB_DAT3 |
paul@0 | 60 | |
paul@0 | 61 | /* MAX3421E definitions. */ |
paul@0 | 62 | |
paul@0 | 63 | #define MAX_REG_READ 0x00 |
paul@0 | 64 | #define MAX_REG_WRITE 0x02 |
paul@0 | 65 | |
paul@13 | 66 | #define MAX_REG_RCVFIFO 1 |
paul@13 | 67 | #define MAX_REG_SNDFIFO 2 |
paul@13 | 68 | #define MAX_REG_SUDFIFO 4 |
paul@13 | 69 | #define MAX_REG_RCVBC 6 |
paul@13 | 70 | #define MAX_REG_SNDBC 7 |
paul@4 | 71 | #define MAX_REG_USBIRQ 13 |
paul@7 | 72 | #define MAX_REG_USBIEN 14 |
paul@0 | 73 | #define MAX_REG_USBCTL 15 |
paul@7 | 74 | #define MAX_REG_CPUCTL 16 |
paul@0 | 75 | #define MAX_REG_PINCTL 17 |
paul@0 | 76 | #define MAX_REG_REVISION 18 |
paul@7 | 77 | #define MAX_REG_HIRQ 25 |
paul@7 | 78 | #define MAX_REG_HIEN 26 |
paul@0 | 79 | #define MAX_REG_MODE 27 |
paul@13 | 80 | #define MAX_REG_PERADDR 28 |
paul@7 | 81 | #define MAX_REG_HCTL 29 |
paul@13 | 82 | #define MAX_REG_HXFR 30 |
paul@0 | 83 | #define MAX_REG_HRSL 31 |
paul@0 | 84 | |
paul@4 | 85 | #define MAX_USBIRQ_OSCOKIRQ 1 |
paul@4 | 86 | #define MAX_USBIRQ_NOVBUSIRQ 32 |
paul@4 | 87 | #define MAX_USBIRQ_VBUSIRQ 64 |
paul@4 | 88 | |
paul@0 | 89 | #define MAX_USBCTL_PWRDOWN 16 |
paul@0 | 90 | #define MAX_USBCTL_CHIPRES 32 |
paul@0 | 91 | |
paul@7 | 92 | #define MAX_CPUCTL_IE 1 |
paul@7 | 93 | |
paul@0 | 94 | #define MAX_PINCTL_POSINT_LOW 0 |
paul@0 | 95 | #define MAX_PINCTL_POSINT_HIGH 4 |
paul@0 | 96 | #define MAX_PINCTL_INTLEVEL_EDGE 0 |
paul@0 | 97 | #define MAX_PINCTL_INTLEVEL_LEVEL 8 |
paul@0 | 98 | #define MAX_PINCTL_FDUPSPI_HALF 0 |
paul@0 | 99 | #define MAX_PINCTL_FDUPSPI_FULL 16 |
paul@0 | 100 | |
paul@7 | 101 | #define MAX_HIRQ_BUSEVENTIRQ 1 |
paul@7 | 102 | #define MAX_HIRQ_RWUIRQ 2 |
paul@7 | 103 | #define MAX_HIRQ_RCVDAVIRQ 4 |
paul@7 | 104 | #define MAX_HIRQ_SNDBAVIRQ 8 |
paul@7 | 105 | #define MAX_HIRQ_SUSDNIRQ 16 |
paul@7 | 106 | #define MAX_HIRQ_CONDETIRQ 32 |
paul@7 | 107 | #define MAX_HIRQ_FRAMEIRQ 64 |
paul@7 | 108 | #define MAX_HIRQ_HXFRDNIRQ 128 |
paul@7 | 109 | |
paul@15 | 110 | #define MAX_HIEN_BUSEVENTIE 1 |
paul@7 | 111 | #define MAX_HIEN_CONDETIE 32 |
paul@15 | 112 | #define MAX_HIEN_FRAMEIE 64 |
paul@7 | 113 | |
paul@0 | 114 | #define MAX_MODE_PERIPHERAL 0 |
paul@0 | 115 | #define MAX_MODE_HOST 1 |
paul@7 | 116 | #define MAX_MODE_LOWSPEED 2 |
paul@7 | 117 | #define MAX_MODE_SOFKAENAB 8 |
paul@0 | 118 | #define MAX_MODE_SEPIRQ_OFF 0 |
paul@0 | 119 | #define MAX_MODE_SEPIRQ_ON 16 |
paul@0 | 120 | #define MAX_MODE_DMPULLDN 64 |
paul@0 | 121 | #define MAX_MODE_DPPULLDN 128 |
paul@0 | 122 | |
paul@12 | 123 | #define MAX_MODE_HOST_ENABLED MAX_MODE_HOST | MAX_MODE_SEPIRQ_OFF | MAX_MODE_DMPULLDN | MAX_MODE_DPPULLDN |
paul@12 | 124 | #define MAX_MODE_HOST_FULLSPEED MAX_MODE_HOST_ENABLED |
paul@12 | 125 | #define MAX_MODE_HOST_LOWSPEED MAX_MODE_HOST_ENABLED | MAX_MODE_LOWSPEED |
paul@12 | 126 | |
paul@15 | 127 | #define MAX_HCTL_BUSRST 1 |
paul@7 | 128 | #define MAX_HCTL_SAMPLEBUS 4 |
paul@13 | 129 | #define MAX_HCTL_RCVTOG0 16 |
paul@13 | 130 | #define MAX_HCTL_RCVTOG1 32 |
paul@13 | 131 | #define MAX_HCTL_SNDTOG0 64 |
paul@13 | 132 | #define MAX_HCTL_SNDTOG1 128 |
paul@13 | 133 | |
paul@13 | 134 | #define MAX_HXFR_SETUP 16 |
paul@13 | 135 | #define MAX_HXFR_OUTNIN 32 |
paul@13 | 136 | #define MAX_HXFR_HS 128 |
paul@7 | 137 | |
paul@7 | 138 | #define MAX_HRSL_JSTATUS 128 |
paul@7 | 139 | #define MAX_HRSL_KSTATUS 64 |
paul@13 | 140 | #define MAX_HRSL_SNDTOGRD 32 |
paul@13 | 141 | #define MAX_HRSL_RCVTOGRD 16 |
paul@13 | 142 | #define MAX_HRSL_HRSLT 15 |
paul@7 | 143 | |
paul@0 | 144 | #define max_reg(n) ((uint8_t) (n << 3)) |
paul@0 | 145 | #define max_reg_read(n) (max_reg(n) | MAX_REG_READ) |
paul@0 | 146 | #define max_reg_write(n) (max_reg(n) | MAX_REG_WRITE) |
paul@0 | 147 | |
paul@0 | 148 | void spi_begin() |
paul@0 | 149 | { |
paul@0 | 150 | CLR(MAX_SS); |
paul@0 | 151 | } |
paul@0 | 152 | |
paul@0 | 153 | void spi_end() |
paul@0 | 154 | { |
paul@0 | 155 | SET(MAX_SS); |
paul@0 | 156 | } |
paul@0 | 157 | |
paul@0 | 158 | /** |
paul@0 | 159 | * Send the given value via MOSI while receiving a value via MISO. |
paul@0 | 160 | * This requires full-duplex SPI and will produce a status value for the first |
paul@0 | 161 | * value sent (the command). |
paul@0 | 162 | */ |
paul@0 | 163 | uint8_t spi_sendrecv(uint8_t v) |
paul@0 | 164 | { |
paul@0 | 165 | uint8_t result = 0; |
paul@0 | 166 | uint8_t mask; |
paul@0 | 167 | |
paul@0 | 168 | for (mask = 0x80; mask; mask >>= 1) |
paul@0 | 169 | { |
paul@0 | 170 | if (v & mask) |
paul@0 | 171 | { |
paul@7 | 172 | #ifdef DEBUG |
paul@0 | 173 | printf("1"); |
paul@7 | 174 | #endif |
paul@0 | 175 | SET(MAX_MOSI); |
paul@0 | 176 | } |
paul@0 | 177 | else |
paul@0 | 178 | { |
paul@7 | 179 | #ifdef DEBUG |
paul@0 | 180 | printf("0"); |
paul@7 | 181 | #endif |
paul@0 | 182 | CLR(MAX_MOSI); |
paul@0 | 183 | } |
paul@0 | 184 | |
paul@0 | 185 | /* Wait for stable output signal. */ |
paul@0 | 186 | |
paul@0 | 187 | SET(MAX_SCLK); |
paul@0 | 188 | |
paul@0 | 189 | if (PIN(MAX_MISO)) |
paul@0 | 190 | result |= mask; |
paul@0 | 191 | |
paul@0 | 192 | CLR(MAX_SCLK); |
paul@0 | 193 | } |
paul@0 | 194 | |
paul@7 | 195 | #ifdef DEBUG |
paul@0 | 196 | printf("\n"); |
paul@7 | 197 | #endif |
paul@0 | 198 | return result; |
paul@0 | 199 | } |
paul@0 | 200 | |
paul@6 | 201 | uint8_t max_read(uint8_t reg, uint8_t *status) |
paul@6 | 202 | { |
paul@6 | 203 | uint8_t result = 0, tmpstatus = 0; |
paul@6 | 204 | |
paul@6 | 205 | tmpstatus = 0; |
paul@6 | 206 | |
paul@6 | 207 | spi_begin(); |
paul@6 | 208 | tmpstatus = spi_sendrecv(max_reg_read(reg)); |
paul@6 | 209 | result = spi_sendrecv(0); |
paul@6 | 210 | spi_end(); |
paul@6 | 211 | |
paul@6 | 212 | if (status != NULL) |
paul@6 | 213 | *status = tmpstatus; |
paul@6 | 214 | |
paul@6 | 215 | return result; |
paul@6 | 216 | } |
paul@6 | 217 | |
paul@6 | 218 | uint8_t max_write(uint8_t reg, uint8_t value) |
paul@6 | 219 | { |
paul@6 | 220 | uint8_t status = 0; |
paul@6 | 221 | |
paul@6 | 222 | spi_begin(); |
paul@6 | 223 | status = spi_sendrecv(max_reg_write(reg)); |
paul@6 | 224 | spi_sendrecv(value); |
paul@6 | 225 | spi_end(); |
paul@6 | 226 | |
paul@6 | 227 | return status; |
paul@6 | 228 | } |
paul@6 | 229 | |
paul@13 | 230 | /** |
paul@13 | 231 | * Return whether data can be sent. |
paul@13 | 232 | */ |
paul@15 | 233 | bool max_can_send(uint8_t *status) |
paul@13 | 234 | { |
paul@15 | 235 | if (status == NULL) |
paul@15 | 236 | return max_read(MAX_REG_HIRQ, NULL) & MAX_HIRQ_SNDBAVIRQ; |
paul@15 | 237 | else |
paul@15 | 238 | return *status & MAX_HIRQ_SNDBAVIRQ; |
paul@13 | 239 | } |
paul@13 | 240 | |
paul@13 | 241 | /** |
paul@13 | 242 | * Set the sending data toggle. |
paul@13 | 243 | */ |
paul@13 | 244 | void max_set_send_toggle(bool toggle) |
paul@13 | 245 | { |
paul@13 | 246 | max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_SNDTOG1 : MAX_HCTL_SNDTOG0); |
paul@13 | 247 | } |
paul@13 | 248 | |
paul@13 | 249 | /** |
paul@13 | 250 | * Return the sending data toggle. |
paul@13 | 251 | */ |
paul@13 | 252 | bool max_get_send_toggle() |
paul@13 | 253 | { |
paul@13 | 254 | return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_SNDTOGRD) != 0; |
paul@13 | 255 | } |
paul@13 | 256 | |
paul@13 | 257 | /** |
paul@13 | 258 | * Set the receiving data toggle. |
paul@13 | 259 | */ |
paul@13 | 260 | void max_set_recv_toggle(bool toggle) |
paul@13 | 261 | { |
paul@13 | 262 | max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_RCVTOG1 : MAX_HCTL_RCVTOG0); |
paul@13 | 263 | } |
paul@13 | 264 | |
paul@13 | 265 | /** |
paul@13 | 266 | * Return the receiving data toggle. |
paul@13 | 267 | */ |
paul@13 | 268 | bool max_get_recv_toggle() |
paul@13 | 269 | { |
paul@13 | 270 | return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_RCVTOGRD) != 0; |
paul@13 | 271 | } |
paul@13 | 272 | |
paul@13 | 273 | /** |
paul@13 | 274 | * Wait for handshake/timeout after a transfer. |
paul@13 | 275 | */ |
paul@13 | 276 | uint8_t max_wait_transfer(uint8_t status) |
paul@13 | 277 | { |
paul@13 | 278 | while (!(status & MAX_HIRQ_HXFRDNIRQ)) |
paul@13 | 279 | { |
paul@13 | 280 | status = max_read(MAX_REG_HIRQ, NULL); |
paul@13 | 281 | } |
paul@13 | 282 | |
paul@13 | 283 | return status; |
paul@13 | 284 | } |
paul@13 | 285 | |
paul@13 | 286 | /** |
paul@13 | 287 | * Send HS payload for control transfers. |
paul@13 | 288 | */ |
paul@13 | 289 | uint8_t max_send_hs() |
paul@13 | 290 | { |
paul@13 | 291 | uint8_t status = max_write(MAX_REG_HXFR, MAX_HXFR_HS); |
paul@13 | 292 | return max_wait_transfer(status); |
paul@13 | 293 | } |
paul@13 | 294 | |
paul@13 | 295 | /** |
paul@13 | 296 | * Write the given data to the FIFO. |
paul@13 | 297 | */ |
paul@13 | 298 | void max_write_fifo(uint8_t endpoint, uint8_t *data, uint8_t len) |
paul@13 | 299 | { |
paul@13 | 300 | uint8_t count; |
paul@13 | 301 | |
paul@13 | 302 | for (count = 0; count < len; count++) |
paul@13 | 303 | { |
paul@13 | 304 | max_write(endpoint ? MAX_REG_SNDFIFO : MAX_REG_SUDFIFO, data[count]); |
paul@13 | 305 | } |
paul@13 | 306 | |
paul@13 | 307 | if (endpoint) |
paul@13 | 308 | max_write(MAX_REG_SNDBC, len); |
paul@13 | 309 | } |
paul@13 | 310 | |
paul@13 | 311 | /** |
paul@13 | 312 | * Read the data from the FIFO. |
paul@13 | 313 | */ |
paul@13 | 314 | void max_read_fifo(uint8_t *data, uint8_t *len, uint8_t *datalimit) |
paul@13 | 315 | { |
paul@13 | 316 | uint8_t count, received = max_read(MAX_REG_RCVBC, NULL); |
paul@13 | 317 | |
paul@13 | 318 | *len += received; |
paul@13 | 319 | |
paul@13 | 320 | for (count = 0; (count < received) && (data < datalimit); count++) |
paul@13 | 321 | { |
paul@13 | 322 | *data++ = max_read(MAX_REG_RCVFIFO, NULL); |
paul@13 | 323 | } |
paul@13 | 324 | } |
paul@13 | 325 | |
paul@13 | 326 | /** |
paul@14 | 327 | * Send a control request to the given address consisting of the given setup |
paul@14 | 328 | * data. |
paul@14 | 329 | */ |
paul@14 | 330 | uint8_t max_control(uint8_t address, uint8_t *setup) |
paul@14 | 331 | { |
paul@14 | 332 | uint8_t status, hrsl = 0; |
paul@14 | 333 | |
paul@15 | 334 | printf("Writing FIFO with setup...\n"); |
paul@14 | 335 | max_write_fifo(0, setup, 8); |
paul@14 | 336 | |
paul@14 | 337 | /* Set the address. */ |
paul@14 | 338 | |
paul@14 | 339 | max_write(MAX_REG_PERADDR, address); |
paul@14 | 340 | |
paul@14 | 341 | /* Initiate the transfer. */ |
paul@14 | 342 | |
paul@14 | 343 | do |
paul@14 | 344 | { |
paul@15 | 345 | printf("Initiating transfer...\n"); |
paul@14 | 346 | status = max_write(MAX_REG_HXFR, MAX_HXFR_SETUP); |
paul@14 | 347 | status = max_wait_transfer(status); |
paul@14 | 348 | hrsl = max_read(MAX_REG_HRSL, &status); |
paul@15 | 349 | printf("HRSL = %x\n", hrsl); |
paul@15 | 350 | sleep(1); |
paul@14 | 351 | } |
paul@15 | 352 | while (hrsl & MAX_HRSL_HRSLT); |
paul@14 | 353 | |
paul@14 | 354 | return status; |
paul@14 | 355 | } |
paul@14 | 356 | |
paul@14 | 357 | /** |
paul@13 | 358 | * Send a request to the given address and endpoint, using the supplied data |
paul@13 | 359 | * payload with the given length, indicating the preserved toggle state of the |
paul@13 | 360 | * endpoint (which will be updated). |
paul@13 | 361 | */ |
paul@13 | 362 | uint8_t max_send(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t len, bool *toggle) |
paul@13 | 363 | { |
paul@13 | 364 | uint8_t status, hrsl = 0; |
paul@13 | 365 | |
paul@13 | 366 | max_write_fifo(endpoint, data, len); |
paul@13 | 367 | |
paul@14 | 368 | if (endpoint) |
paul@14 | 369 | max_set_send_toggle(*toggle); |
paul@13 | 370 | |
paul@13 | 371 | /* Set the address. */ |
paul@13 | 372 | |
paul@13 | 373 | max_write(MAX_REG_PERADDR, address); |
paul@13 | 374 | |
paul@13 | 375 | /* Initiate the transfer. */ |
paul@13 | 376 | |
paul@13 | 377 | do |
paul@13 | 378 | { |
paul@14 | 379 | status = max_write(MAX_REG_HXFR, endpoint | MAX_HXFR_OUTNIN); |
paul@13 | 380 | status = max_wait_transfer(status); |
paul@13 | 381 | |
paul@13 | 382 | /* Test for usable data. */ |
paul@13 | 383 | |
paul@13 | 384 | if (!(status & MAX_HIRQ_SNDBAVIRQ)) |
paul@13 | 385 | continue; |
paul@13 | 386 | |
paul@13 | 387 | hrsl = max_read(MAX_REG_HRSL, &status); |
paul@13 | 388 | } |
paul@15 | 389 | while (hrsl & MAX_HRSL_HRSLT); |
paul@13 | 390 | |
paul@14 | 391 | if (endpoint) |
paul@14 | 392 | *toggle = max_get_send_toggle(); |
paul@13 | 393 | |
paul@13 | 394 | return status; |
paul@13 | 395 | } |
paul@13 | 396 | |
paul@13 | 397 | /** |
paul@13 | 398 | * Make a request for data from the given address and endpoint, collecting it in |
paul@13 | 399 | * the supplied buffer with the given length, indicating the preserved toggle |
paul@14 | 400 | * state of the endpoint (which will be updated) The length will be updated to |
paul@14 | 401 | * indicate the total length of the received data. |
paul@13 | 402 | */ |
paul@14 | 403 | uint8_t max_recv(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t *len, bool *toggle) |
paul@13 | 404 | { |
paul@13 | 405 | uint8_t *datalimit = data + *len; |
paul@13 | 406 | uint8_t status, hrsl = 0; |
paul@13 | 407 | |
paul@14 | 408 | if (endpoint) |
paul@14 | 409 | max_set_send_toggle(*toggle); |
paul@13 | 410 | |
paul@13 | 411 | /* Set the address. */ |
paul@13 | 412 | |
paul@13 | 413 | max_write(MAX_REG_PERADDR, address); |
paul@13 | 414 | |
paul@13 | 415 | /* Initiate the transfer. */ |
paul@13 | 416 | |
paul@13 | 417 | do |
paul@13 | 418 | { |
paul@13 | 419 | status = max_write(MAX_REG_HXFR, endpoint); |
paul@13 | 420 | status = max_wait_transfer(status); |
paul@13 | 421 | |
paul@13 | 422 | /* Test for usable data. */ |
paul@13 | 423 | |
paul@13 | 424 | if (!(status & MAX_HIRQ_RCVDAVIRQ)) |
paul@13 | 425 | continue; |
paul@13 | 426 | |
paul@13 | 427 | hrsl = max_read(MAX_REG_HRSL, &status); |
paul@13 | 428 | } |
paul@15 | 429 | while (hrsl & MAX_HRSL_HRSLT); |
paul@13 | 430 | |
paul@13 | 431 | do |
paul@13 | 432 | { |
paul@13 | 433 | max_read_fifo(data, len, datalimit); |
paul@13 | 434 | |
paul@13 | 435 | /* Indicate that all data has been read. */ |
paul@13 | 436 | |
paul@13 | 437 | status = max_write(MAX_REG_HIRQ, MAX_HIRQ_RCVDAVIRQ); |
paul@13 | 438 | } |
paul@13 | 439 | while (status & MAX_HIRQ_RCVDAVIRQ); |
paul@13 | 440 | |
paul@14 | 441 | if (endpoint) |
paul@14 | 442 | *toggle = max_get_send_toggle(); |
paul@13 | 443 | |
paul@13 | 444 | return status; |
paul@13 | 445 | } |
paul@13 | 446 | |
paul@3 | 447 | void chipreset() |
paul@3 | 448 | { |
paul@3 | 449 | printf("Resetting...\n"); |
paul@6 | 450 | max_write(MAX_REG_USBCTL, MAX_USBCTL_CHIPRES); |
paul@3 | 451 | |
paul@3 | 452 | printf("Clearing the reset...\n"); |
paul@6 | 453 | max_write(MAX_REG_USBCTL, 0); |
paul@3 | 454 | } |
paul@3 | 455 | |
paul@4 | 456 | uint8_t check() |
paul@4 | 457 | { |
paul@6 | 458 | uint8_t oscillator; |
paul@4 | 459 | |
paul@6 | 460 | oscillator = max_read(MAX_REG_USBIRQ, NULL); |
paul@4 | 461 | |
paul@4 | 462 | return (oscillator & ~(MAX_USBIRQ_NOVBUSIRQ | MAX_USBIRQ_VBUSIRQ)) == MAX_USBIRQ_OSCOKIRQ; |
paul@4 | 463 | } |
paul@4 | 464 | |
paul@7 | 465 | uint8_t wait() |
paul@7 | 466 | { |
paul@7 | 467 | uint16_t timeout = 1024; |
paul@7 | 468 | |
paul@7 | 469 | /* Wait for the oscillator before performing USB activity. */ |
paul@7 | 470 | |
paul@7 | 471 | printf("Waiting...\n"); |
paul@7 | 472 | |
paul@7 | 473 | while ((timeout > 0) && (!check())) |
paul@7 | 474 | { |
paul@7 | 475 | timeout--; |
paul@7 | 476 | } |
paul@7 | 477 | |
paul@7 | 478 | printf("Iterations remaining: %d\n", timeout); |
paul@7 | 479 | |
paul@7 | 480 | return timeout; |
paul@7 | 481 | } |
paul@7 | 482 | |
paul@11 | 483 | uint8_t samplebusready() |
paul@7 | 484 | { |
paul@7 | 485 | uint8_t result; |
paul@7 | 486 | |
paul@7 | 487 | result = max_read(MAX_REG_HCTL, NULL); |
paul@7 | 488 | |
paul@7 | 489 | return !(result & MAX_HCTL_SAMPLEBUS); |
paul@7 | 490 | } |
paul@7 | 491 | |
paul@11 | 492 | void samplebus() |
paul@11 | 493 | { |
paul@11 | 494 | max_write(MAX_REG_HCTL, MAX_HCTL_SAMPLEBUS); |
paul@11 | 495 | while (!samplebusready()); |
paul@11 | 496 | } |
paul@11 | 497 | |
paul@13 | 498 | /** |
paul@13 | 499 | * Handle the connection or disconnection of a device, returning true if the |
paul@13 | 500 | * device is now connected or false otherwise. |
paul@13 | 501 | */ |
paul@13 | 502 | bool devicechanged() |
paul@11 | 503 | { |
paul@11 | 504 | uint8_t hrsl, mode; |
paul@11 | 505 | |
paul@11 | 506 | hrsl = max_read(MAX_REG_HRSL, NULL); |
paul@11 | 507 | mode = max_read(MAX_REG_MODE, NULL); |
paul@11 | 508 | |
paul@11 | 509 | if ((hrsl & MAX_HRSL_JSTATUS) && (hrsl & MAX_HRSL_KSTATUS)) |
paul@11 | 510 | { |
paul@11 | 511 | printf("Bad device status.\n"); |
paul@11 | 512 | } |
paul@11 | 513 | else if (!(hrsl & MAX_HRSL_JSTATUS) && !(hrsl & MAX_HRSL_KSTATUS)) |
paul@11 | 514 | { |
paul@11 | 515 | printf("Device disconnected.\n"); |
paul@11 | 516 | } |
paul@11 | 517 | else |
paul@11 | 518 | { |
paul@11 | 519 | printf("Device connected.\n"); |
paul@11 | 520 | |
paul@11 | 521 | /* Low speed device when J and lowspeed have the same level. |
paul@11 | 522 | Since J and K should have opposing levels, K can be tested when |
paul@11 | 523 | lowspeed is low. */ |
paul@11 | 524 | |
paul@11 | 525 | if (((hrsl & MAX_HRSL_JSTATUS) && (mode & MAX_MODE_LOWSPEED)) || |
paul@11 | 526 | ((hrsl & MAX_HRSL_KSTATUS) && !(mode & MAX_MODE_LOWSPEED))) |
paul@11 | 527 | { |
paul@11 | 528 | printf("Device is low speed.\n"); |
paul@12 | 529 | max_write(MAX_REG_MODE, MAX_MODE_HOST_LOWSPEED); |
paul@11 | 530 | } |
paul@11 | 531 | else |
paul@11 | 532 | { |
paul@11 | 533 | printf("Device is full speed.\n"); |
paul@12 | 534 | max_write(MAX_REG_MODE, MAX_MODE_HOST_FULLSPEED); |
paul@11 | 535 | } |
paul@13 | 536 | |
paul@15 | 537 | /* Reset the device. */ |
paul@15 | 538 | |
paul@15 | 539 | max_write(MAX_REG_HCTL, MAX_HCTL_BUSRST); |
paul@13 | 540 | return true; |
paul@11 | 541 | } |
paul@13 | 542 | |
paul@13 | 543 | return false; |
paul@13 | 544 | } |
paul@13 | 545 | |
paul@13 | 546 | void setup_packet(uint8_t *setup, uint8_t request_type, uint8_t request, uint16_t value, uint16_t index, uint16_t length) |
paul@13 | 547 | { |
paul@13 | 548 | setup[0] = request_type; |
paul@13 | 549 | setup[1] = request; |
paul@13 | 550 | setup[2] = value & 0xff; |
paul@13 | 551 | setup[3] = value >> 8; |
paul@13 | 552 | setup[4] = index & 0xff; |
paul@13 | 553 | setup[5] = index >> 8; |
paul@13 | 554 | setup[6] = length & 0xff; |
paul@13 | 555 | setup[7] = length >> 8; |
paul@11 | 556 | } |
paul@11 | 557 | |
paul@15 | 558 | bool max_init_device(bool *in_toggle) |
paul@15 | 559 | { |
paul@15 | 560 | uint8_t data[64], len = 64, setup[8]; |
paul@15 | 561 | struct usb_device_descriptor *desc; |
paul@15 | 562 | |
paul@15 | 563 | printf("Sending control request to address 0, endpoint 0...\n"); |
paul@15 | 564 | setup_packet(setup, USB_ENDPOINT_IN, USB_REQ_GET_DESCRIPTOR, USB_DT_DEVICE, 0, USB_DT_DEVICE_SIZE); |
paul@15 | 565 | max_control(0, setup); |
paul@15 | 566 | max_recv(0, 0, data, &len, in_toggle); |
paul@15 | 567 | |
paul@15 | 568 | if (len >= sizeof(struct usb_device_descriptor)) |
paul@15 | 569 | { |
paul@15 | 570 | desc = (struct usb_device_descriptor *) data; |
paul@15 | 571 | printf("bLength: %d\n", desc->bLength); |
paul@15 | 572 | printf("bDescriptorType: %d\n", desc->bDescriptorType); |
paul@15 | 573 | printf("bcdUSB: %d\n", desc->bcdUSB); |
paul@15 | 574 | printf("bDeviceClass: %d\n", desc->bDeviceClass); |
paul@15 | 575 | printf("bDeviceSubClass: %d\n", desc->bDeviceSubClass); |
paul@15 | 576 | printf("bDeviceProtocol: %d\n", desc->bDeviceProtocol); |
paul@15 | 577 | printf("bMaxPacketSize0: %d\n", desc->bMaxPacketSize0); |
paul@15 | 578 | printf("idVendor: %x\n", desc->idVendor); |
paul@15 | 579 | printf("idProduct: %x\n", desc->idProduct); |
paul@15 | 580 | printf("bcdDevice: %d\n", desc->bcdDevice); |
paul@15 | 581 | printf("iManufacturer: %d\n", desc->iManufacturer); |
paul@15 | 582 | printf("iProduct: %d\n", desc->iProduct); |
paul@15 | 583 | printf("iSerialNumber: %d\n", desc->iSerialNumber); |
paul@15 | 584 | printf("bNumConfigurations: %d\n", desc->bNumConfigurations); |
paul@15 | 585 | return true; |
paul@15 | 586 | } |
paul@15 | 587 | |
paul@15 | 588 | return false; |
paul@15 | 589 | } |
paul@15 | 590 | |
paul@8 | 591 | void shutdown(int signum) |
paul@8 | 592 | { |
paul@8 | 593 | printf("Closing...\n"); |
paul@8 | 594 | ubb_close(0); |
paul@8 | 595 | exit(1); |
paul@8 | 596 | } |
paul@8 | 597 | |
paul@0 | 598 | int main(int argc, char *argv[]) |
paul@0 | 599 | { |
paul@8 | 600 | uint8_t status = 0, revision = 0; |
paul@7 | 601 | uint16_t count; |
paul@13 | 602 | bool in_toggle = 0; |
paul@15 | 603 | max_devstate devstate = MAX_DEVSTATE_INIT; |
paul@0 | 604 | |
paul@8 | 605 | signal(SIGINT, &shutdown); |
paul@8 | 606 | |
paul@0 | 607 | if (ubb_open(0) < 0) { |
paul@0 | 608 | perror("ubb_open"); |
paul@0 | 609 | return 1; |
paul@0 | 610 | } |
paul@0 | 611 | |
paul@0 | 612 | ubb_power(1); |
paul@0 | 613 | printf("Power on.\n"); |
paul@0 | 614 | |
paul@0 | 615 | OUT(MAX_SS); |
paul@0 | 616 | OUT(MAX_MOSI); |
paul@0 | 617 | OUT(MAX_SCLK); |
paul@0 | 618 | OUT(MAX_RESET); |
paul@0 | 619 | IN(MAX_INT); |
paul@0 | 620 | IN(MAX_MISO); |
paul@0 | 621 | |
paul@0 | 622 | /* Initialise SPI. */ |
paul@7 | 623 | /* Set SS# to 1. */ |
paul@0 | 624 | |
paul@0 | 625 | SET(MAX_SS); |
paul@0 | 626 | CLR(MAX_MOSI); |
paul@0 | 627 | CLR(MAX_SCLK); |
paul@7 | 628 | SET(MAX_RESET); |
paul@0 | 629 | |
paul@0 | 630 | /* Initialise the MAX3421E. */ |
paul@0 | 631 | |
paul@0 | 632 | /* Set full-duplex, interrupt signalling. */ |
paul@0 | 633 | |
paul@0 | 634 | printf("Setting pin control...\n"); |
paul@6 | 635 | max_write(MAX_REG_PINCTL, MAX_PINCTL_INTLEVEL_LEVEL | MAX_PINCTL_FDUPSPI_FULL); |
paul@0 | 636 | |
paul@3 | 637 | chipreset(); |
paul@7 | 638 | printf("Ready? %d\n", wait()); |
paul@7 | 639 | |
paul@7 | 640 | /* Check various registers. */ |
paul@7 | 641 | |
paul@7 | 642 | printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); |
paul@7 | 643 | printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); |
paul@0 | 644 | |
paul@0 | 645 | /* Set host mode. */ |
paul@0 | 646 | |
paul@0 | 647 | printf("Setting mode...\n"); |
paul@12 | 648 | status = max_write(MAX_REG_MODE, MAX_MODE_HOST_ENABLED); |
paul@7 | 649 | |
paul@7 | 650 | printf("Setting INT signalling...\n"); |
paul@7 | 651 | status = max_write(MAX_REG_CPUCTL, MAX_CPUCTL_IE); |
paul@7 | 652 | |
paul@15 | 653 | printf("Setting event signalling...\n"); |
paul@15 | 654 | status = max_write(MAX_REG_HIEN, MAX_HIEN_CONDETIE | MAX_HIEN_FRAMEIE | MAX_HIEN_BUSEVENTIE); |
paul@7 | 655 | |
paul@7 | 656 | /* Check various registers. */ |
paul@7 | 657 | |
paul@7 | 658 | printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); |
paul@7 | 659 | printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); |
paul@7 | 660 | printf("IE: %x\n", max_read(MAX_REG_HIEN, &status)); |
paul@7 | 661 | printf("CPU: %x\n", max_read(MAX_REG_CPUCTL, &status)); |
paul@7 | 662 | printf("Pin: %x\n", max_read(MAX_REG_PINCTL, &status)); |
paul@7 | 663 | printf("USBIRQ: %x\n", max_read(MAX_REG_USBIRQ, &status)); |
paul@7 | 664 | printf("USBIE: %x\n", max_read(MAX_REG_USBIEN, &status)); |
paul@0 | 665 | |
paul@0 | 666 | /* Read from the REVISION register. */ |
paul@0 | 667 | |
paul@0 | 668 | printf("Reading...\n"); |
paul@6 | 669 | revision = max_read(MAX_REG_REVISION, &status); |
paul@0 | 670 | printf("Revision = %x\n", revision); |
paul@7 | 671 | |
paul@8 | 672 | for (count = 0; count <= 65535; count++) |
paul@7 | 673 | { |
paul@8 | 674 | if (!PIN(MAX_INT)) |
paul@7 | 675 | { |
paul@9 | 676 | status = max_read(MAX_REG_HIRQ, NULL); |
paul@9 | 677 | |
paul@15 | 678 | if (status & MAX_HIRQ_BUSEVENTIRQ) |
paul@15 | 679 | printf("Bus "); |
paul@15 | 680 | if (status & MAX_HIRQ_RCVDAVIRQ) |
paul@15 | 681 | printf("Data "); |
paul@15 | 682 | if (status & MAX_HIRQ_SUSDNIRQ) |
paul@15 | 683 | printf("Suspended "); |
paul@15 | 684 | if (status & MAX_HIRQ_CONDETIRQ) |
paul@15 | 685 | printf("Connection "); |
paul@15 | 686 | if (status & MAX_HIRQ_FRAMEIRQ) |
paul@15 | 687 | printf("Frame "); |
paul@15 | 688 | printf("\n"); |
paul@15 | 689 | |
paul@15 | 690 | /* Detect device connection/disconnection. */ |
paul@15 | 691 | |
paul@15 | 692 | if ((devstate == MAX_DEVSTATE_INIT) && (status & MAX_HIRQ_CONDETIRQ) && devicechanged()) |
paul@13 | 693 | { |
paul@15 | 694 | devstate = MAX_DEVSTATE_CONNECTED; |
paul@13 | 695 | } |
paul@15 | 696 | |
paul@15 | 697 | /* Handle device reset initiation. */ |
paul@15 | 698 | |
paul@15 | 699 | else if ((devstate == MAX_DEVSTATE_CONNECTED) && (status & MAX_HIRQ_BUSEVENTIRQ)) |
paul@15 | 700 | { |
paul@15 | 701 | status = max_write(MAX_REG_MODE, max_read(MAX_REG_MODE, NULL) | MAX_MODE_SOFKAENAB); |
paul@15 | 702 | devstate = MAX_DEVSTATE_RESET; |
paul@15 | 703 | } |
paul@15 | 704 | |
paul@15 | 705 | /* Handle device reset completion, initiating communications. */ |
paul@15 | 706 | |
paul@15 | 707 | else if ((devstate == MAX_DEVSTATE_RESET) && (status & MAX_HIRQ_FRAMEIRQ) && max_can_send(&status)) |
paul@15 | 708 | { |
paul@15 | 709 | max_init_device(&in_toggle); |
paul@15 | 710 | devstate = MAX_DEVSTATE_READY; |
paul@15 | 711 | status = max_write(MAX_REG_HIEN, MAX_HIEN_CONDETIE | MAX_HIEN_BUSEVENTIE); |
paul@15 | 712 | } |
paul@7 | 713 | |
paul@8 | 714 | max_write(MAX_REG_HIRQ, status); |
paul@7 | 715 | } |
paul@7 | 716 | } |
paul@0 | 717 | |
paul@0 | 718 | printf("Closing...\n"); |
paul@0 | 719 | ubb_close(0); |
paul@0 | 720 | |
paul@0 | 721 | return 0; |
paul@0 | 722 | } |