1 /* 2 * Ben NanoNote and Arduino USB Host shield communication. 3 * 4 * Copyright 2013 Paul Boddie 5 * 6 * SPI functions derived from those in lib/atben.c by Werner Almesberger: 7 * 8 * Copyright 2010-2011 Werner Almesberger 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #include <ubb/ubb.h> 17 #include <stdio.h> 18 #include <signal.h> 19 #include <stdlib.h> 20 #include <usb.h> 21 22 /* Found in Python's asdl.h. */ 23 24 #ifndef __cplusplus 25 typedef enum {false, true} bool; 26 #endif 27 28 /* Pin assignments: 29 * 30 * Sniffer UBB Shield 31 * ------- ---- ------ 32 * DAT2 DAT2 9 (INT) 33 * CD DAT3 10 (SS) 34 * CMD CMD 7 (RESET) 35 * VCC VDD VIN 36 * CLK CLK 13 (SCLK) 37 * GND GND GND 38 * DAT0 DAT0 11 (MOSI) 39 * DAT1 DAT1 12 (MISO) 40 * 8 (GPX) (not assigned) 41 */ 42 43 #define MAX_RESET UBB_CMD 44 #define MAX_SCLK UBB_CLK 45 #define MAX_MOSI UBB_DAT0 46 #define MAX_MISO UBB_DAT1 47 #define MAX_INT UBB_DAT2 48 #define MAX_SS UBB_DAT3 49 50 /* MAX3421E definitions. */ 51 52 #define MAX_REG_READ 0x00 53 #define MAX_REG_WRITE 0x02 54 55 #define MAX_REG_RCVFIFO 1 56 #define MAX_REG_SNDFIFO 2 57 #define MAX_REG_SUDFIFO 4 58 #define MAX_REG_RCVBC 6 59 #define MAX_REG_SNDBC 7 60 #define MAX_REG_USBIRQ 13 61 #define MAX_REG_USBIEN 14 62 #define MAX_REG_USBCTL 15 63 #define MAX_REG_CPUCTL 16 64 #define MAX_REG_PINCTL 17 65 #define MAX_REG_REVISION 18 66 #define MAX_REG_HIRQ 25 67 #define MAX_REG_HIEN 26 68 #define MAX_REG_MODE 27 69 #define MAX_REG_PERADDR 28 70 #define MAX_REG_HCTL 29 71 #define MAX_REG_HXFR 30 72 #define MAX_REG_HRSL 31 73 74 #define MAX_USBIRQ_OSCOKIRQ 1 75 #define MAX_USBIRQ_NOVBUSIRQ 32 76 #define MAX_USBIRQ_VBUSIRQ 64 77 78 #define MAX_USBCTL_PWRDOWN 16 79 #define MAX_USBCTL_CHIPRES 32 80 81 #define MAX_CPUCTL_IE 1 82 83 #define MAX_PINCTL_POSINT_LOW 0 84 #define MAX_PINCTL_POSINT_HIGH 4 85 #define MAX_PINCTL_INTLEVEL_EDGE 0 86 #define MAX_PINCTL_INTLEVEL_LEVEL 8 87 #define MAX_PINCTL_FDUPSPI_HALF 0 88 #define MAX_PINCTL_FDUPSPI_FULL 16 89 90 #define MAX_HIRQ_BUSEVENTIRQ 1 91 #define MAX_HIRQ_RWUIRQ 2 92 #define MAX_HIRQ_RCVDAVIRQ 4 93 #define MAX_HIRQ_SNDBAVIRQ 8 94 #define MAX_HIRQ_SUSDNIRQ 16 95 #define MAX_HIRQ_CONDETIRQ 32 96 #define MAX_HIRQ_FRAMEIRQ 64 97 #define MAX_HIRQ_HXFRDNIRQ 128 98 99 #define MAX_HIEN_CONDETIE 32 100 101 #define MAX_MODE_PERIPHERAL 0 102 #define MAX_MODE_HOST 1 103 #define MAX_MODE_LOWSPEED 2 104 #define MAX_MODE_SOFKAENAB 8 105 #define MAX_MODE_SEPIRQ_OFF 0 106 #define MAX_MODE_SEPIRQ_ON 16 107 #define MAX_MODE_DMPULLDN 64 108 #define MAX_MODE_DPPULLDN 128 109 110 #define MAX_MODE_HOST_ENABLED MAX_MODE_HOST | MAX_MODE_SEPIRQ_OFF | MAX_MODE_DMPULLDN | MAX_MODE_DPPULLDN 111 #define MAX_MODE_HOST_FULLSPEED MAX_MODE_HOST_ENABLED 112 #define MAX_MODE_HOST_LOWSPEED MAX_MODE_HOST_ENABLED | MAX_MODE_LOWSPEED 113 114 #define MAX_HCTL_SAMPLEBUS 4 115 #define MAX_HCTL_RCVTOG0 16 116 #define MAX_HCTL_RCVTOG1 32 117 #define MAX_HCTL_SNDTOG0 64 118 #define MAX_HCTL_SNDTOG1 128 119 120 #define MAX_HXFR_SETUP 16 121 #define MAX_HXFR_OUTNIN 32 122 #define MAX_HXFR_HS 128 123 124 #define MAX_HRSL_JSTATUS 128 125 #define MAX_HRSL_KSTATUS 64 126 #define MAX_HRSL_SNDTOGRD 32 127 #define MAX_HRSL_RCVTOGRD 16 128 #define MAX_HRSL_HRSLT 15 129 130 #define max_reg(n) ((uint8_t) (n << 3)) 131 #define max_reg_read(n) (max_reg(n) | MAX_REG_READ) 132 #define max_reg_write(n) (max_reg(n) | MAX_REG_WRITE) 133 134 void spi_begin() 135 { 136 CLR(MAX_SS); 137 } 138 139 void spi_end() 140 { 141 SET(MAX_SS); 142 } 143 144 /** 145 * Send the given value via MOSI while receiving a value via MISO. 146 * This requires full-duplex SPI and will produce a status value for the first 147 * value sent (the command). 148 */ 149 uint8_t spi_sendrecv(uint8_t v) 150 { 151 uint8_t result = 0; 152 uint8_t mask; 153 154 for (mask = 0x80; mask; mask >>= 1) 155 { 156 if (v & mask) 157 { 158 #ifdef DEBUG 159 printf("1"); 160 #endif 161 SET(MAX_MOSI); 162 } 163 else 164 { 165 #ifdef DEBUG 166 printf("0"); 167 #endif 168 CLR(MAX_MOSI); 169 } 170 171 /* Wait for stable output signal. */ 172 173 SET(MAX_SCLK); 174 175 if (PIN(MAX_MISO)) 176 result |= mask; 177 178 CLR(MAX_SCLK); 179 } 180 181 #ifdef DEBUG 182 printf("\n"); 183 #endif 184 return result; 185 } 186 187 uint8_t max_read(uint8_t reg, uint8_t *status) 188 { 189 uint8_t result = 0, tmpstatus = 0; 190 191 tmpstatus = 0; 192 193 spi_begin(); 194 tmpstatus = spi_sendrecv(max_reg_read(reg)); 195 result = spi_sendrecv(0); 196 spi_end(); 197 198 if (status != NULL) 199 *status = tmpstatus; 200 201 return result; 202 } 203 204 uint8_t max_write(uint8_t reg, uint8_t value) 205 { 206 uint8_t status = 0; 207 208 spi_begin(); 209 status = spi_sendrecv(max_reg_write(reg)); 210 spi_sendrecv(value); 211 spi_end(); 212 213 return status; 214 } 215 216 /** 217 * Return whether data can be sent. 218 */ 219 bool max_can_send() 220 { 221 uint8_t status = max_read(MAX_REG_HIRQ, NULL); 222 223 return !(status & MAX_HIRQ_SNDBAVIRQ); 224 } 225 226 /** 227 * Set the sending data toggle. 228 */ 229 void max_set_send_toggle(bool toggle) 230 { 231 max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_SNDTOG1 : MAX_HCTL_SNDTOG0); 232 } 233 234 /** 235 * Return the sending data toggle. 236 */ 237 bool max_get_send_toggle() 238 { 239 return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_SNDTOGRD) != 0; 240 } 241 242 /** 243 * Set the receiving data toggle. 244 */ 245 void max_set_recv_toggle(bool toggle) 246 { 247 max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_RCVTOG1 : MAX_HCTL_RCVTOG0); 248 } 249 250 /** 251 * Return the receiving data toggle. 252 */ 253 bool max_get_recv_toggle() 254 { 255 return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_RCVTOGRD) != 0; 256 } 257 258 /** 259 * Wait for handshake/timeout after a transfer. 260 */ 261 uint8_t max_wait_transfer(uint8_t status) 262 { 263 while (!(status & MAX_HIRQ_HXFRDNIRQ)) 264 { 265 status = max_read(MAX_REG_HIRQ, NULL); 266 } 267 268 return status; 269 } 270 271 /** 272 * Send HS payload for control transfers. 273 */ 274 uint8_t max_send_hs() 275 { 276 uint8_t status = max_write(MAX_REG_HXFR, MAX_HXFR_HS); 277 return max_wait_transfer(status); 278 } 279 280 /** 281 * Write the given data to the FIFO. 282 */ 283 void max_write_fifo(uint8_t endpoint, uint8_t *data, uint8_t len) 284 { 285 uint8_t count; 286 287 for (count = 0; count < len; count++) 288 { 289 max_write(endpoint ? MAX_REG_SNDFIFO : MAX_REG_SUDFIFO, data[count]); 290 } 291 292 if (endpoint) 293 max_write(MAX_REG_SNDBC, len); 294 } 295 296 /** 297 * Read the data from the FIFO. 298 */ 299 void max_read_fifo(uint8_t *data, uint8_t *len, uint8_t *datalimit) 300 { 301 uint8_t count, received = max_read(MAX_REG_RCVBC, NULL); 302 303 *len += received; 304 305 for (count = 0; (count < received) && (data < datalimit); count++) 306 { 307 *data++ = max_read(MAX_REG_RCVFIFO, NULL); 308 } 309 } 310 311 /** 312 * Send a request to the given address and endpoint, using the supplied data 313 * payload with the given length, indicating the preserved toggle state of the 314 * endpoint (which will be updated). 315 */ 316 uint8_t max_send(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t len, bool *toggle) 317 { 318 uint8_t status, hrsl = 0; 319 320 max_write_fifo(endpoint, data, len); 321 322 max_set_send_toggle(*toggle); 323 324 /* Set the address. */ 325 326 max_write(MAX_REG_PERADDR, address); 327 328 /* Initiate the transfer. */ 329 330 do 331 { 332 status = max_write(MAX_REG_HXFR, endpoint | MAX_HXFR_OUTNIN | (endpoint ? 0 : MAX_HXFR_SETUP)); 333 status = max_wait_transfer(status); 334 335 /* Test for usable data. */ 336 337 if (!(status & MAX_HIRQ_SNDBAVIRQ)) 338 continue; 339 340 hrsl = max_read(MAX_REG_HRSL, &status); 341 } 342 while ((hrsl & MAX_HRSL_HRSLT) != 0); 343 344 *toggle = max_get_send_toggle(); 345 346 return status; 347 } 348 349 /** 350 * Make a request for data from the given address and endpoint, collecting it in 351 * the supplied buffer with the given length, indicating the preserved toggle 352 * state of the endpoint (which will be updated), and providing optional setup 353 * data (for control transfers). The length will be updated to indicate the 354 * total length of the received data. 355 */ 356 uint8_t max_recv(uint8_t address, uint8_t endpoint, uint8_t *data, uint8_t *len, bool *toggle, uint8_t *setup) 357 { 358 uint8_t *datalimit = data + *len; 359 uint8_t status, hrsl = 0; 360 361 /* Write control transfer information, if appropriate. */ 362 363 if (!endpoint) 364 max_write_fifo(endpoint, setup, 8); 365 366 max_set_send_toggle(*toggle); 367 368 /* Set the address. */ 369 370 max_write(MAX_REG_PERADDR, address); 371 372 /* Initiate the transfer. */ 373 374 do 375 { 376 status = max_write(MAX_REG_HXFR, endpoint); 377 status = max_wait_transfer(status); 378 379 /* Test for usable data. */ 380 381 if (!(status & MAX_HIRQ_RCVDAVIRQ)) 382 continue; 383 384 hrsl = max_read(MAX_REG_HRSL, &status); 385 } 386 while ((hrsl & MAX_HRSL_HRSLT) != 0); 387 388 do 389 { 390 max_read_fifo(data, len, datalimit); 391 392 /* Indicate that all data has been read. */ 393 394 status = max_write(MAX_REG_HIRQ, MAX_HIRQ_RCVDAVIRQ); 395 } 396 while (status & MAX_HIRQ_RCVDAVIRQ); 397 398 *toggle = max_get_send_toggle(); 399 400 return status; 401 } 402 403 void chipreset() 404 { 405 printf("Resetting...\n"); 406 max_write(MAX_REG_USBCTL, MAX_USBCTL_CHIPRES); 407 408 printf("Clearing the reset...\n"); 409 max_write(MAX_REG_USBCTL, 0); 410 } 411 412 uint8_t check() 413 { 414 uint8_t oscillator; 415 416 oscillator = max_read(MAX_REG_USBIRQ, NULL); 417 418 return (oscillator & ~(MAX_USBIRQ_NOVBUSIRQ | MAX_USBIRQ_VBUSIRQ)) == MAX_USBIRQ_OSCOKIRQ; 419 } 420 421 uint8_t wait() 422 { 423 uint16_t timeout = 1024; 424 425 /* Wait for the oscillator before performing USB activity. */ 426 427 printf("Waiting...\n"); 428 429 while ((timeout > 0) && (!check())) 430 { 431 timeout--; 432 } 433 434 printf("Iterations remaining: %d\n", timeout); 435 436 return timeout; 437 } 438 439 uint8_t samplebusready() 440 { 441 uint8_t result; 442 443 result = max_read(MAX_REG_HCTL, NULL); 444 445 return !(result & MAX_HCTL_SAMPLEBUS); 446 } 447 448 void samplebus() 449 { 450 max_write(MAX_REG_HCTL, MAX_HCTL_SAMPLEBUS); 451 while (!samplebusready()); 452 } 453 454 /** 455 * Handle the connection or disconnection of a device, returning true if the 456 * device is now connected or false otherwise. 457 */ 458 bool devicechanged() 459 { 460 uint8_t hrsl, mode; 461 462 hrsl = max_read(MAX_REG_HRSL, NULL); 463 mode = max_read(MAX_REG_MODE, NULL); 464 465 if ((hrsl & MAX_HRSL_JSTATUS) && (hrsl & MAX_HRSL_KSTATUS)) 466 { 467 printf("Bad device status.\n"); 468 } 469 else if (!(hrsl & MAX_HRSL_JSTATUS) && !(hrsl & MAX_HRSL_KSTATUS)) 470 { 471 printf("Device disconnected.\n"); 472 } 473 else 474 { 475 printf("Device connected.\n"); 476 477 /* Low speed device when J and lowspeed have the same level. 478 Since J and K should have opposing levels, K can be tested when 479 lowspeed is low. */ 480 481 if (((hrsl & MAX_HRSL_JSTATUS) && (mode & MAX_MODE_LOWSPEED)) || 482 ((hrsl & MAX_HRSL_KSTATUS) && !(mode & MAX_MODE_LOWSPEED))) 483 { 484 printf("Device is low speed.\n"); 485 max_write(MAX_REG_MODE, MAX_MODE_HOST_LOWSPEED); 486 } 487 else 488 { 489 printf("Device is full speed.\n"); 490 max_write(MAX_REG_MODE, MAX_MODE_HOST_FULLSPEED); 491 } 492 493 return true; 494 } 495 496 return false; 497 } 498 499 void setup_packet(uint8_t *setup, uint8_t request_type, uint8_t request, uint16_t value, uint16_t index, uint16_t length) 500 { 501 setup[0] = request_type; 502 setup[1] = request; 503 setup[2] = value & 0xff; 504 setup[3] = value >> 8; 505 setup[4] = index & 0xff; 506 setup[5] = index >> 8; 507 setup[6] = length & 0xff; 508 setup[7] = length >> 8; 509 } 510 511 void shutdown(int signum) 512 { 513 printf("Closing...\n"); 514 ubb_close(0); 515 exit(1); 516 } 517 518 int main(int argc, char *argv[]) 519 { 520 uint8_t status = 0, revision = 0; 521 uint16_t count; 522 bool in_toggle = 0; 523 uint8_t data[64], len = 64, setup[8]; 524 525 signal(SIGINT, &shutdown); 526 527 if (ubb_open(0) < 0) { 528 perror("ubb_open"); 529 return 1; 530 } 531 532 ubb_power(1); 533 printf("Power on.\n"); 534 535 OUT(MAX_SS); 536 OUT(MAX_MOSI); 537 OUT(MAX_SCLK); 538 OUT(MAX_RESET); 539 IN(MAX_INT); 540 IN(MAX_MISO); 541 542 /* Initialise SPI. */ 543 /* Set SS# to 1. */ 544 545 SET(MAX_SS); 546 CLR(MAX_MOSI); 547 CLR(MAX_SCLK); 548 SET(MAX_RESET); 549 550 /* Initialise the MAX3421E. */ 551 552 /* Set full-duplex, interrupt signalling. */ 553 554 printf("Setting pin control...\n"); 555 max_write(MAX_REG_PINCTL, MAX_PINCTL_INTLEVEL_LEVEL | MAX_PINCTL_FDUPSPI_FULL); 556 557 chipreset(); 558 printf("Ready? %d\n", wait()); 559 560 /* Check various registers. */ 561 562 printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); 563 printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); 564 565 /* Set host mode. */ 566 567 printf("Setting mode...\n"); 568 status = max_write(MAX_REG_MODE, MAX_MODE_HOST_ENABLED); 569 570 printf("Setting INT signalling...\n"); 571 status = max_write(MAX_REG_CPUCTL, MAX_CPUCTL_IE); 572 573 printf("Setting connection signalling...\n"); 574 status = max_write(MAX_REG_HIEN, MAX_HIEN_CONDETIE); 575 576 /* Check various registers. */ 577 578 printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); 579 printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); 580 printf("IE: %x\n", max_read(MAX_REG_HIEN, &status)); 581 printf("CPU: %x\n", max_read(MAX_REG_CPUCTL, &status)); 582 printf("Pin: %x\n", max_read(MAX_REG_PINCTL, &status)); 583 printf("USBIRQ: %x\n", max_read(MAX_REG_USBIRQ, &status)); 584 printf("USBIE: %x\n", max_read(MAX_REG_USBIEN, &status)); 585 586 /* Read from the REVISION register. */ 587 588 printf("Reading...\n"); 589 revision = max_read(MAX_REG_REVISION, &status); 590 printf("Revision = %x\n", revision); 591 592 for (count = 0; count <= 65535; count++) 593 { 594 if (!PIN(MAX_INT)) 595 { 596 status = max_read(MAX_REG_HIRQ, NULL); 597 598 if ((status & MAX_HIRQ_CONDETIRQ) && devicechanged() && max_can_send()) 599 { 600 printf("Sending control request to address 0, endpoint 0...\n"); 601 setup_packet(setup, USB_ENDPOINT_IN, USB_REQ_GET_DESCRIPTOR, USB_DT_DEVICE, 0, USB_DT_DEVICE_SIZE); 602 max_recv(0, 0, data, &len, &in_toggle, setup); 603 } 604 if (status & MAX_HIRQ_SUSDNIRQ) 605 printf("Suspend done.\n"); 606 if (status & MAX_HIRQ_BUSEVENTIRQ) 607 printf("Bus event.\n"); 608 if (status & MAX_HIRQ_RCVDAVIRQ) 609 printf("Data received.\n"); 610 611 max_write(MAX_REG_HIRQ, status); 612 } 613 } 614 615 printf("Closing...\n"); 616 ubb_close(0); 617 618 return 0; 619 }