1 /* 2 * Ben NanoNote and Arduino USB Host shield communication. 3 * 4 * Copyright 2013 Paul Boddie 5 * 6 * SPI functions derived from those in lib/atben.c by Werner Almesberger: 7 * 8 * Copyright 2010-2011 Werner Almesberger 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #include <ubb/ubb.h> 17 #include <stdio.h> 18 #include <signal.h> 19 #include <stdlib.h> 20 #include <usb.h> 21 #include <unistd.h> 22 #include <string.h> 23 #include <endian.h> 24 25 /* Found in Python's asdl.h. */ 26 27 #ifndef __cplusplus 28 typedef enum {false, true} bool; 29 #endif 30 31 /* Initialisation states. */ 32 33 typedef enum 34 { 35 MAX_DEVSTATE_INIT = 0, 36 MAX_DEVSTATE_CONNECTED = 1, 37 MAX_DEVSTATE_RESET = 2, 38 MAX_DEVSTATE_INSPECTED = 3, 39 MAX_DEVSTATE_RESET_AGAIN = 4, 40 MAX_DEVSTATE_READY = 5 41 } max_devstate; 42 43 /* Device details. */ 44 45 typedef struct 46 { 47 bool in_toggle, out_toggle; 48 struct usb_device_descriptor desc; 49 } max_device; 50 51 /* Pin assignments: 52 * 53 * Sniffer UBB Shield 54 * ------- ---- ------ 55 * DAT2 DAT2 9 (INT) 56 * CD DAT3 10 (SS) 57 * CMD CMD 7 (RESET) 58 * VCC VDD VIN 59 * CLK CLK 13 (SCLK) 60 * GND GND GND 61 * DAT0 DAT0 11 (MOSI) 62 * DAT1 DAT1 12 (MISO) 63 * 8 (GPX) (not assigned) 64 */ 65 66 #define MAX_RESET UBB_CMD 67 #define MAX_SCLK UBB_CLK 68 #define MAX_MOSI UBB_DAT0 69 #define MAX_MISO UBB_DAT1 70 #define MAX_INT UBB_DAT2 71 #define MAX_SS UBB_DAT3 72 73 /* MAX3421E definitions. */ 74 75 #define MAX_REG_READ 0x00 76 #define MAX_REG_WRITE 0x02 77 78 #define MAX_REG_RCVFIFO 1 79 #define MAX_REG_SNDFIFO 2 80 #define MAX_REG_SUDFIFO 4 81 #define MAX_REG_RCVBC 6 82 #define MAX_REG_SNDBC 7 83 #define MAX_REG_USBIRQ 13 84 #define MAX_REG_USBIEN 14 85 #define MAX_REG_USBCTL 15 86 #define MAX_REG_CPUCTL 16 87 #define MAX_REG_PINCTL 17 88 #define MAX_REG_REVISION 18 89 #define MAX_REG_HIRQ 25 90 #define MAX_REG_HIEN 26 91 #define MAX_REG_MODE 27 92 #define MAX_REG_PERADDR 28 93 #define MAX_REG_HCTL 29 94 #define MAX_REG_HXFR 30 95 #define MAX_REG_HRSL 31 96 97 #define MAX_USBIRQ_OSCOKIRQ 1 98 #define MAX_USBIRQ_NOVBUSIRQ 32 99 #define MAX_USBIRQ_VBUSIRQ 64 100 101 #define MAX_USBCTL_PWRDOWN 16 102 #define MAX_USBCTL_CHIPRES 32 103 104 #define MAX_CPUCTL_IE 1 105 106 #define MAX_PINCTL_POSINT_LOW 0 107 #define MAX_PINCTL_POSINT_HIGH 4 108 #define MAX_PINCTL_INTLEVEL_EDGE 0 109 #define MAX_PINCTL_INTLEVEL_LEVEL 8 110 #define MAX_PINCTL_FDUPSPI_HALF 0 111 #define MAX_PINCTL_FDUPSPI_FULL 16 112 113 #define MAX_HIRQ_BUSEVENTIRQ 1 114 #define MAX_HIRQ_RWUIRQ 2 115 #define MAX_HIRQ_RCVDAVIRQ 4 116 #define MAX_HIRQ_SNDBAVIRQ 8 117 #define MAX_HIRQ_SUSDNIRQ 16 118 #define MAX_HIRQ_CONDETIRQ 32 119 #define MAX_HIRQ_FRAMEIRQ 64 120 #define MAX_HIRQ_HXFRDNIRQ 128 121 122 #define MAX_HIEN_BUSEVENTIE 1 123 #define MAX_HIEN_CONDETIE 32 124 #define MAX_HIEN_FRAMEIE 64 125 126 #define MAX_MODE_PERIPHERAL 0 127 #define MAX_MODE_HOST 1 128 #define MAX_MODE_LOWSPEED 2 129 #define MAX_MODE_SOFKAENAB 8 130 #define MAX_MODE_SEPIRQ_OFF 0 131 #define MAX_MODE_SEPIRQ_ON 16 132 #define MAX_MODE_DMPULLDN 64 133 #define MAX_MODE_DPPULLDN 128 134 135 #define MAX_MODE_HOST_ENABLED MAX_MODE_HOST | MAX_MODE_SEPIRQ_OFF | MAX_MODE_DMPULLDN | MAX_MODE_DPPULLDN 136 #define MAX_MODE_HOST_FULLSPEED MAX_MODE_HOST_ENABLED 137 #define MAX_MODE_HOST_LOWSPEED MAX_MODE_HOST_ENABLED | MAX_MODE_LOWSPEED 138 139 #define MAX_HCTL_BUSRST 1 140 #define MAX_HCTL_SAMPLEBUS 4 141 #define MAX_HCTL_RCVTOG0 16 142 #define MAX_HCTL_RCVTOG1 32 143 #define MAX_HCTL_SNDTOG0 64 144 #define MAX_HCTL_SNDTOG1 128 145 146 #define MAX_HXFR_SETUP 16 147 #define MAX_HXFR_OUTNIN 32 148 #define MAX_HXFR_HS 128 149 150 #define MAX_HRSL_JSTATUS 128 151 #define MAX_HRSL_KSTATUS 64 152 #define MAX_HRSL_SNDTOGRD 32 153 #define MAX_HRSL_RCVTOGRD 16 154 #define MAX_HRSL_HRSLT 15 155 156 #define max_reg(n) ((uint8_t) (n << 3)) 157 #define max_reg_read(n) (max_reg(n) | MAX_REG_READ) 158 #define max_reg_write(n) (max_reg(n) | MAX_REG_WRITE) 159 160 void spi_begin() 161 { 162 CLR(MAX_SS); 163 } 164 165 void spi_end() 166 { 167 SET(MAX_SS); 168 } 169 170 /** 171 * Send the given value via MOSI while receiving a value via MISO. 172 * This requires full-duplex SPI and will produce a status value for the first 173 * value sent (the command). 174 */ 175 uint8_t spi_sendrecv(uint8_t v) 176 { 177 uint8_t result = 0; 178 uint8_t mask; 179 180 for (mask = 0x80; mask; mask >>= 1) 181 { 182 if (v & mask) 183 { 184 #ifdef DEBUG 185 printf("1"); 186 #endif 187 SET(MAX_MOSI); 188 } 189 else 190 { 191 #ifdef DEBUG 192 printf("0"); 193 #endif 194 CLR(MAX_MOSI); 195 } 196 197 /* Wait for stable output signal. */ 198 199 SET(MAX_SCLK); 200 201 if (PIN(MAX_MISO)) 202 result |= mask; 203 204 CLR(MAX_SCLK); 205 } 206 207 #ifdef DEBUG 208 printf("\n"); 209 #endif 210 return result; 211 } 212 213 uint8_t max_read(uint8_t reg, uint8_t *status) 214 { 215 uint8_t result = 0, tmpstatus = 0; 216 217 tmpstatus = 0; 218 219 spi_begin(); 220 tmpstatus = spi_sendrecv(max_reg_read(reg)); 221 result = spi_sendrecv(0); 222 spi_end(); 223 224 if (status != NULL) 225 *status = tmpstatus; 226 227 return result; 228 } 229 230 uint8_t max_write(uint8_t reg, uint8_t value) 231 { 232 uint8_t status = 0; 233 234 spi_begin(); 235 status = spi_sendrecv(max_reg_write(reg)); 236 spi_sendrecv(value); 237 spi_end(); 238 239 return status; 240 } 241 242 /** 243 * Return whether data can be sent. 244 */ 245 bool max_can_send(uint8_t *status) 246 { 247 if (status == NULL) 248 return max_read(MAX_REG_HIRQ, NULL) & MAX_HIRQ_SNDBAVIRQ; 249 else 250 return *status & MAX_HIRQ_SNDBAVIRQ; 251 } 252 253 /** 254 * Set the sending data toggle. 255 */ 256 void max_set_send_toggle(bool toggle) 257 { 258 max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_SNDTOG1 : MAX_HCTL_SNDTOG0); 259 } 260 261 /** 262 * Return the sending data toggle. 263 */ 264 bool max_get_send_toggle() 265 { 266 return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_SNDTOGRD) != 0; 267 } 268 269 /** 270 * Set the receiving data toggle. 271 */ 272 void max_set_recv_toggle(bool toggle) 273 { 274 max_write(MAX_REG_HCTL, toggle ? MAX_HCTL_RCVTOG1 : MAX_HCTL_RCVTOG0); 275 } 276 277 /** 278 * Return the receiving data toggle. 279 */ 280 bool max_get_recv_toggle() 281 { 282 return (max_read(MAX_REG_HRSL, NULL) & MAX_HRSL_RCVTOGRD) != 0; 283 } 284 285 /** 286 * Wait for handshake/timeout after a transfer. 287 */ 288 uint8_t max_wait_transfer(uint8_t status) 289 { 290 while (!(status & MAX_HIRQ_HXFRDNIRQ)) 291 { 292 status = max_read(MAX_REG_HIRQ, NULL); 293 } 294 295 max_write(MAX_REG_HIRQ, MAX_HIRQ_HXFRDNIRQ); 296 return max_read(MAX_REG_HIRQ, NULL); 297 } 298 299 /** 300 * Write the given data to the FIFO. 301 */ 302 void max_write_fifo(uint8_t endpoint, uint8_t *data, uint8_t len) 303 { 304 uint8_t count; 305 306 for (count = 0; count < len; count++) 307 { 308 max_write(endpoint ? MAX_REG_SNDFIFO : MAX_REG_SUDFIFO, data[count]); 309 } 310 311 if (endpoint) 312 max_write(MAX_REG_SNDBC, len); 313 } 314 315 /** 316 * Read the data from the FIFO. 317 */ 318 void max_read_fifo(uint8_t **data, uint8_t *len, uint8_t *datalimit) 319 { 320 uint8_t count, received = max_read(MAX_REG_RCVBC, NULL); 321 printf("Received %d bytes.\n", received); 322 323 *len += received; 324 325 for (count = 0; (count < received) && (*data < datalimit); count++) 326 { 327 *((*data)++) = max_read(MAX_REG_RCVFIFO, NULL); 328 } 329 } 330 331 /** 332 * Send a control request consisting of the given setup data. 333 */ 334 uint8_t max_control(uint8_t *setup) 335 { 336 uint8_t status, hrsl; 337 338 max_write_fifo(0, setup, 8); 339 340 /* Initiate the transfer. */ 341 342 do 343 { 344 status = max_write(MAX_REG_HXFR, MAX_HXFR_SETUP); 345 status = max_wait_transfer(status); 346 hrsl = max_read(MAX_REG_HRSL, &status); 347 } 348 while (hrsl & MAX_HRSL_HRSLT); 349 350 return status; 351 } 352 353 /** 354 * Perform a status transaction as part of a larger control transaction. 355 * The out parameter is used to indicate the kind of status transfer to be 356 * performed and should be the inverse of the control transfer direction. 357 */ 358 uint8_t max_control_status(bool out) 359 { 360 uint8_t status, hrsl; 361 362 do 363 { 364 status = max_write(MAX_REG_HXFR, MAX_HXFR_HS | (out ? MAX_HXFR_OUTNIN : 0)); 365 status = max_wait_transfer(status); 366 hrsl = max_read(MAX_REG_HRSL, &status); 367 } 368 while (hrsl & MAX_HRSL_HRSLT); 369 370 return status; 371 } 372 373 /** 374 * Send a request to the given endpoint, using the supplied data payload with 375 * the given length, indicating the preserved toggle state of the endpoint 376 * (which will be updated). 377 */ 378 uint8_t max_send(uint8_t endpoint, uint8_t *data, uint8_t len, bool *toggle) 379 { 380 uint8_t status, hrsl = 0; 381 382 max_write_fifo(endpoint, data, len); 383 384 max_set_send_toggle(*toggle); 385 386 /* Initiate the transfer. */ 387 388 do 389 { 390 status = max_write(MAX_REG_HXFR, endpoint | MAX_HXFR_OUTNIN); 391 status = max_wait_transfer(status); 392 393 /* Test for usable data. */ 394 395 if (status & MAX_HIRQ_SNDBAVIRQ) 396 { 397 hrsl = max_read(MAX_REG_HRSL, &status); 398 399 if (!(hrsl & MAX_HRSL_HRSLT)) 400 break; 401 } 402 } 403 while (true); 404 405 *toggle = max_get_send_toggle(); 406 407 return status; 408 } 409 410 /** 411 * Make a request for data from the given endpoint, collecting it in the 412 * supplied buffer with the given length, indicating the preserved toggle state 413 * of the endpoint (which will be updated). The length will be updated to 414 * indicate the total length of the received data. 415 */ 416 bool max_recv(uint8_t endpoint, uint8_t *data, uint8_t *len, bool *toggle) 417 { 418 uint8_t *datalimit = data + *len; 419 uint8_t status, hrsl = 0; 420 uint16_t attempt = 1024; 421 422 max_set_recv_toggle(*toggle); 423 424 /* Initiate the transfer. */ 425 426 do 427 { 428 status = max_write(MAX_REG_HXFR, endpoint); 429 status = max_wait_transfer(status); 430 431 /* Test for usable data. */ 432 433 hrsl = max_read(MAX_REG_HRSL, &status); 434 435 attempt--; 436 } 437 while ((hrsl & MAX_HRSL_HRSLT) && attempt); 438 439 if (!attempt) 440 { 441 printf("HRSL is %x\n", hrsl); 442 return false; 443 } 444 445 while (status & MAX_HIRQ_RCVDAVIRQ) 446 { 447 max_read_fifo(&data, len, datalimit); 448 449 /* Indicate that all data has been read. */ 450 451 max_write(MAX_REG_HIRQ, MAX_HIRQ_RCVDAVIRQ); 452 status = max_read(MAX_REG_HIRQ, NULL); 453 } 454 455 *toggle = max_get_recv_toggle(); 456 457 return true; 458 } 459 460 void chipreset() 461 { 462 printf("Resetting...\n"); 463 max_write(MAX_REG_USBCTL, MAX_USBCTL_CHIPRES); 464 465 printf("Clearing the reset...\n"); 466 max_write(MAX_REG_USBCTL, 0); 467 } 468 469 uint8_t check() 470 { 471 uint8_t oscillator; 472 473 oscillator = max_read(MAX_REG_USBIRQ, NULL); 474 475 return (oscillator & ~(MAX_USBIRQ_NOVBUSIRQ | MAX_USBIRQ_VBUSIRQ)) == MAX_USBIRQ_OSCOKIRQ; 476 } 477 478 uint8_t wait() 479 { 480 uint16_t timeout = 1024; 481 482 /* Wait for the oscillator before performing USB activity. */ 483 484 printf("Waiting...\n"); 485 486 while ((timeout > 0) && (!check())) 487 { 488 timeout--; 489 } 490 491 printf("Iterations remaining: %d\n", timeout); 492 493 return timeout; 494 } 495 496 /** 497 * Return whether the bus is ready to be sampled. The application note claims 498 * that the SAMPLEBUS bit is cleared, but this does not seem to be the case. 499 */ 500 uint8_t samplebusready() 501 { 502 uint8_t result; 503 504 result = max_read(MAX_REG_HCTL, NULL); 505 return result & MAX_HCTL_SAMPLEBUS; 506 } 507 508 void samplebus() 509 { 510 max_write(MAX_REG_HCTL, MAX_HCTL_SAMPLEBUS); 511 while (!samplebusready()); 512 } 513 514 /** 515 * Handle the connection or disconnection of a device, returning true if the 516 * device is now connected or false otherwise. If the device is connected, a 517 * bus reset is performed. 518 */ 519 bool devicechanged() 520 { 521 uint8_t hrsl, mode; 522 523 hrsl = max_read(MAX_REG_HRSL, NULL); 524 mode = max_read(MAX_REG_MODE, NULL); 525 526 if ((hrsl & MAX_HRSL_JSTATUS) && (hrsl & MAX_HRSL_KSTATUS)) 527 { 528 printf("Bad device status.\n"); 529 } 530 else if (!(hrsl & MAX_HRSL_JSTATUS) && !(hrsl & MAX_HRSL_KSTATUS)) 531 { 532 printf("Device disconnected.\n"); 533 } 534 else 535 { 536 printf("Device connected.\n"); 537 538 /* Low speed device when J and lowspeed have the same level. 539 Since J and K should have opposing levels, K can be tested when 540 lowspeed is low. */ 541 542 if (((hrsl & MAX_HRSL_JSTATUS) && (mode & MAX_MODE_LOWSPEED)) || 543 ((hrsl & MAX_HRSL_KSTATUS) && !(mode & MAX_MODE_LOWSPEED))) 544 { 545 printf("Device is low speed.\n"); 546 max_write(MAX_REG_MODE, MAX_MODE_HOST_LOWSPEED); 547 } 548 else 549 { 550 printf("Device is full speed.\n"); 551 max_write(MAX_REG_MODE, MAX_MODE_HOST_FULLSPEED); 552 } 553 554 /* Reset the device. */ 555 556 max_write(MAX_REG_HCTL, MAX_HCTL_BUSRST); 557 return true; 558 } 559 560 return false; 561 } 562 563 void setup_packet(uint8_t *setup, uint8_t request_type, uint8_t request, uint16_t value, uint16_t index, uint16_t length) 564 { 565 setup[0] = request_type; 566 setup[1] = request; 567 setup[2] = value & 0xff; 568 setup[3] = value >> 8; 569 setup[4] = index & 0xff; 570 setup[5] = index >> 8; 571 setup[6] = length & 0xff; 572 setup[7] = length >> 8; 573 } 574 575 bool max_init_device(max_device *device) 576 { 577 uint8_t data[64], len = 64, setup[8]; 578 579 printf("Sending control request to address 0, endpoint 0...\n"); 580 581 max_write(MAX_REG_PERADDR, 0); 582 setup_packet(setup, USB_ENDPOINT_IN, USB_REQ_GET_DESCRIPTOR, USB_DT_DEVICE << 8, 0, USB_DT_DEVICE_SIZE); 583 max_control(setup); 584 device->in_toggle = true; 585 if (!max_recv(0, data, &len, &device->in_toggle)) 586 return false; 587 max_control_status(true); 588 589 if (len >= sizeof(struct usb_device_descriptor)) 590 { 591 memcpy(&device->desc, data, sizeof(struct usb_device_descriptor)); 592 device->desc.bcdUSB = le16toh(device->desc.bcdUSB); 593 device->desc.idVendor = le16toh(device->desc.idVendor); 594 device->desc.idProduct = le16toh(device->desc.idProduct); 595 device->desc.bcdDevice = le16toh(device->desc.bcdDevice); 596 597 printf("bLength: %d\n", device->desc.bLength); 598 printf("bDescriptorType: %d\n", device->desc.bDescriptorType); 599 printf("bcdUSB: %04x\n", device->desc.bcdUSB); 600 printf("bDeviceClass: %d\n", device->desc.bDeviceClass); 601 printf("bDeviceSubClass: %d\n", device->desc.bDeviceSubClass); 602 printf("bDeviceProtocol: %d\n", device->desc.bDeviceProtocol); 603 printf("bMaxPacketSize0: %d\n", device->desc.bMaxPacketSize0); 604 printf("idVendor: %04x\n", device->desc.idVendor); 605 printf("idProduct: %04x\n", device->desc.idProduct); 606 printf("bcdDevice: %04x\n", device->desc.bcdDevice); 607 printf("iManufacturer: %d\n", device->desc.iManufacturer); 608 printf("iProduct: %d\n", device->desc.iProduct); 609 printf("iSerialNumber: %d\n", device->desc.iSerialNumber); 610 printf("bNumConfigurations: %d\n", device->desc.bNumConfigurations); 611 612 /* Reset the device. */ 613 614 max_write(MAX_REG_HCTL, MAX_HCTL_BUSRST); 615 return true; 616 } 617 618 return false; 619 } 620 621 void shutdown(int signum) 622 { 623 printf("Closing...\n"); 624 ubb_close(0); 625 exit(1); 626 } 627 628 int main(int argc, char *argv[]) 629 { 630 uint8_t status = 0, revision = 0; 631 uint16_t count; 632 bool bus_event, data_event, suspended_event, connection_event, frame_event; 633 max_device device; 634 max_devstate devstate = MAX_DEVSTATE_INIT; 635 636 device.in_toggle = false; 637 device.out_toggle = false; 638 639 signal(SIGINT, &shutdown); 640 641 if (ubb_open(0) < 0) { 642 perror("ubb_open"); 643 return 1; 644 } 645 646 ubb_power(1); 647 printf("Power on.\n"); 648 649 OUT(MAX_SS); 650 OUT(MAX_MOSI); 651 OUT(MAX_SCLK); 652 OUT(MAX_RESET); 653 IN(MAX_INT); 654 IN(MAX_MISO); 655 656 /* Initialise SPI. */ 657 /* Set SS# to 1. */ 658 659 SET(MAX_SS); 660 CLR(MAX_MOSI); 661 CLR(MAX_SCLK); 662 SET(MAX_RESET); 663 664 /* Initialise the MAX3421E. */ 665 666 /* Set full-duplex, interrupt signalling. */ 667 668 printf("Setting pin control...\n"); 669 max_write(MAX_REG_PINCTL, MAX_PINCTL_INTLEVEL_LEVEL | MAX_PINCTL_FDUPSPI_FULL); 670 671 chipreset(); 672 printf("Ready? %d\n", wait()); 673 674 /* Check various registers. */ 675 676 printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); 677 printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); 678 679 /* Set host mode. */ 680 681 printf("Setting mode...\n"); 682 status = max_write(MAX_REG_MODE, MAX_MODE_HOST_ENABLED); 683 684 printf("Setting INT signalling...\n"); 685 status = max_write(MAX_REG_CPUCTL, MAX_CPUCTL_IE); 686 687 printf("Setting event signalling...\n"); 688 status = max_write(MAX_REG_HIEN, MAX_HIEN_CONDETIE | MAX_HIEN_FRAMEIE | MAX_HIEN_BUSEVENTIE); 689 690 /* Check various registers. */ 691 692 printf("Mode: %x\n", max_read(MAX_REG_MODE, &status)); 693 printf("IRQ: %x\n", max_read(MAX_REG_HIRQ, &status)); 694 printf("IE: %x\n", max_read(MAX_REG_HIEN, &status)); 695 printf("CPU: %x\n", max_read(MAX_REG_CPUCTL, &status)); 696 printf("Pin: %x\n", max_read(MAX_REG_PINCTL, &status)); 697 printf("USBIRQ: %x\n", max_read(MAX_REG_USBIRQ, &status)); 698 printf("USBIE: %x\n", max_read(MAX_REG_USBIEN, &status)); 699 700 /* Read from the REVISION register. */ 701 702 printf("Reading...\n"); 703 revision = max_read(MAX_REG_REVISION, &status); 704 printf("Revision = %x\n", revision); 705 706 /* Sample the bus for any devices that are already connected. */ 707 708 samplebus(); 709 710 if (devicechanged()) 711 { 712 devstate = MAX_DEVSTATE_CONNECTED; 713 } 714 715 /* Enter the main processing loop. */ 716 717 for (count = 0; count <= 65535; count++) 718 { 719 if (!PIN(MAX_INT)) 720 { 721 /* Obtain interrupt conditions. */ 722 723 status = max_read(MAX_REG_HIRQ, NULL); 724 725 bus_event = status & MAX_HIRQ_BUSEVENTIRQ; 726 data_event = status & MAX_HIRQ_RCVDAVIRQ; 727 suspended_event = status & MAX_HIRQ_SUSDNIRQ; 728 connection_event = status & MAX_HIRQ_CONDETIRQ; 729 frame_event = status & MAX_HIRQ_FRAMEIRQ; 730 731 #ifdef DEBUG 732 if (bus_event) printf("Bus "); 733 if (data_event) printf("Data "); 734 if (suspended_event) printf("Suspended "); 735 if (connection_event) printf("Connection "); 736 if (frame_event) printf("Frame "); 737 printf("\n"); 738 #endif 739 740 /* Acknowledge the interrupts. */ 741 742 max_write(MAX_REG_HIRQ, status); 743 744 /* Detect device connection/disconnection. */ 745 746 if ((devstate == MAX_DEVSTATE_INIT) && connection_event && devicechanged()) 747 { 748 devstate = MAX_DEVSTATE_CONNECTED; 749 printf("CONNECTED\n"); 750 } 751 752 /* Handle device reset initiation. */ 753 754 else if ((devstate == MAX_DEVSTATE_CONNECTED) && bus_event) 755 { 756 max_write(MAX_REG_MODE, max_read(MAX_REG_MODE, NULL) | MAX_MODE_SOFKAENAB); 757 devstate = MAX_DEVSTATE_RESET; 758 printf("RESET\n"); 759 } 760 761 /* Handle device reset completion, getting device details and 762 initiating a second reset. */ 763 764 else if ((devstate == MAX_DEVSTATE_RESET) && frame_event && max_can_send(&status)) 765 { 766 if (max_init_device(&device)) 767 { 768 devstate = MAX_DEVSTATE_INSPECTED; 769 printf("INSPECTED\n"); 770 } 771 else 772 printf("FAILED: RESET -> INSPECTED\n"); 773 } 774 775 /* Handle the second device reset initiation. */ 776 777 else if ((devstate == MAX_DEVSTATE_INSPECTED) && bus_event) 778 { 779 devstate = MAX_DEVSTATE_RESET_AGAIN; 780 printf("RESET AGAIN\n"); 781 } 782 783 /* Handle the second device reset completion, initiating communications. */ 784 785 else if ((devstate == MAX_DEVSTATE_RESET_AGAIN) && frame_event && max_can_send(&status)) 786 { 787 max_write(MAX_REG_MODE, max_read(MAX_REG_MODE, NULL) & ~MAX_MODE_SOFKAENAB); 788 devstate = MAX_DEVSTATE_READY; 789 printf("READY\n"); 790 } 791 792 /* Handle device disconnection. */ 793 794 else if ((devstate != MAX_DEVSTATE_INIT) && connection_event) 795 { 796 devstate = MAX_DEVSTATE_INIT; 797 printf("INIT\n"); 798 } 799 } 800 } 801 802 printf("Closing...\n"); 803 ubb_close(0); 804 805 return 0; 806 }